From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04A7FC43334 for ; Mon, 18 Jul 2022 10:22:43 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 36BC38401F; Mon, 18 Jul 2022 12:22:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 350DF8402E; Mon, 18 Jul 2022 12:22:39 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id D98BA8402F for ; Mon, 18 Jul 2022 12:22:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 94C541042; Mon, 18 Jul 2022 03:22:35 -0700 (PDT) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 88CB03F70D; Mon, 18 Jul 2022 03:22:34 -0700 (PDT) Date: Mon, 18 Jul 2022 11:22:32 +0100 From: Andre Przywara To: Icenowy Zheng Cc: Jagan Teki , Jesse Taube , u-boot@lists.denx.de Subject: Re: [PATCH sunxi/next] spi: sunxi: use XCH status to detect in-progress transfer Message-ID: <20220718112232.354074bb@donnerap.cambridge.arm.com> In-Reply-To: <20220628064924.390103-1-uwu@icenowy.me> References: <20220628064924.390103-1-uwu@icenowy.me> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tue, 28 Jun 2022 14:49:24 +0800 Icenowy Zheng wrote: Hi Icenowy, many thanks for the patch! > The current detection of RX FIFO depth seems to be not reliable, and > XCH will self-clear when a transfer is done. > > Check XCH bit when polling for transfer finish. So as mentioned in the other reply, there are still issues in the SPI driver, some problems being more general. However this patch looks right, and seems like the more robust solution than counting bytes in the FIFO, so I will take it. > Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Applied to sunxi/master. Thanks, Andre > --- > drivers/spi/spi-sunxi.c | 14 +++++--------- > 1 file changed, 5 insertions(+), 9 deletions(-) > > diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c > index 2f33337725..a424c6a98e 100644 > --- a/drivers/spi/spi-sunxi.c > +++ b/drivers/spi/spi-sunxi.c > @@ -83,7 +83,7 @@ DECLARE_GLOBAL_DATA_PTR; > #endif > #define SUN4I_SPI_MIN_RATE 3000 > #define SUN4I_SPI_DEFAULT_RATE 1000000 > -#define SUN4I_SPI_TIMEOUT_US 1000000 > +#define SUN4I_SPI_TIMEOUT_MS 1000 > > #define SPI_REG(priv, reg) ((priv)->base + \ > (priv)->variant->regs[reg]) > @@ -326,7 +326,6 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, > struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); > > u32 len = bitlen / 8; > - u32 rx_fifocnt; > u8 nbytes; > int ret; > > @@ -364,13 +363,10 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, > setbits_le32(SPI_REG(priv, SPI_TCR), > SPI_BIT(priv, SPI_TCR_XCH)); > > - /* Wait till RX FIFO to be empty */ > - ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR), > - rx_fifocnt, > - (((rx_fifocnt & > - SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >> > - SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes), > - SUN4I_SPI_TIMEOUT_US); > + /* Wait for the transfer to be done */ > + ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR), > + SPI_BIT(priv, SPI_TCR_XCH), > + false, SUN4I_SPI_TIMEOUT_MS, false); > if (ret < 0) { > printf("ERROR: sun4i_spi: Timeout transferring data\n"); > sun4i_spi_set_cs(bus, slave_plat->cs, false);