From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F281C19F2B for ; Wed, 27 Jul 2022 13:00:41 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3235E83F8E; Wed, 27 Jul 2022 15:00:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="ONe3ynpS"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9CD4683445; Wed, 27 Jul 2022 15:00:37 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 11FF583FAE for ; Wed, 27 Jul 2022 15:00:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kabel@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id B47A3B82161; Wed, 27 Jul 2022 13:00:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5CB3BC433D7; Wed, 27 Jul 2022 13:00:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658926833; bh=MIVReRDUCdZvzGRCGYFMX2haSvoTdEnM9oqSQWGwaow=; h=From:To:Cc:Subject:Date:From; b=ONe3ynpS6z3iL87SfE7GOibqL3SfZaLYfqlNUIzfItI3hLbFZjrDsL5rl4qGusUkh dwZ0AG/h08szAoB9s51VBbQfP8tevWkM7iVPgQQ8ATo2/olkv3kHFMq2LNp3DO0ZtG OOB3eatS32U1zRvxFY1/AyrYqeP9TAYifoTT6mBx6B1FxdZyb2ssUSEFrAiFEycQm5 qahWD7OlnRtVxw+RQT7skCVVMmLdgY86U+3I2rsQ7OTxKGKYEJorpgGAkkpxEEGp6P Jd+4Mylik+FydHPl9fWTuU8qwb4MGWIwAoo8DGIxcAEf5N/Z26QGFV9zYuP5bZGtw/ doBfhBnnumAOQ== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Stefan Roese Cc: pali@kernel.org, u-boot@lists.denx.de, =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH u-boot-marvell] arm: mvebu: turris_omnia: Fix mpp26 pin name and comment Date: Wed, 27 Jul 2022 15:00:27 +0200 Message-Id: <20220727130027.21247-1-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, which is routed to CN11 pin header, is documented as SPI CS1, but MPP[26] pin does not support this function. Instead it controls chip select 2 if in "spi0" mode. Fix the name of the pin node in pinctrl node and fix the comment in SPI node. Signed-off-by: Marek Behún --- The same patch is being sent to linux, https://lore.kernel.org/linux-arm-kernel/20220727125610.20782-1-kabel@kernel.org/ --- arch/arm/dts/armada-385-turris-omnia.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/armada-385-turris-omnia.dts b/arch/arm/dts/armada-385-turris-omnia.dts index 7f1478edfd..617522be17 100644 --- a/arch/arm/dts/armada-385-turris-omnia.dts +++ b/arch/arm/dts/armada-385-turris-omnia.dts @@ -345,7 +345,7 @@ marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; }; @@ -380,7 +380,7 @@ }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 { -- 2.35.1