From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B34AC04A68 for ; Wed, 27 Jul 2022 15:21:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 06A9F83FA5; Wed, 27 Jul 2022 17:21:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="RTuSdX8N"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1658D84007; Wed, 27 Jul 2022 17:21:43 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 81C818341C for ; Wed, 27 Jul 2022 17:21:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1FB2EB821AB for ; Wed, 27 Jul 2022 15:21:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A317DC433C1 for ; Wed, 27 Jul 2022 15:21:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658935298; bh=GzGwFwN1s5BgOHhwgcyswsD88oEqCRaqCocwv77FeDs=; h=From:To:Subject:Date:From; b=RTuSdX8N8JhNJ70ZA+J7b8X7LA1RGu/0Mn6l4OyprnvcMzK94y/4WUtwADi35Fiv+ gph3iPJotlvljuXwar9r4v3ZLCT4DRwypBLmjPF3bCsEy1nIaDIp3xWTb6TSm5RSnu uSt/Y9EMBttZsRV/CVXGH390FyVtwfMi7laUK203873lugfFdQiXZNevkK7EB6HkR/ Af7g/SlPYRFqz4zBPO3InKECFB5D/bRR20zvf78yswF7rtmsWTSkkkkl23NYSeFSDo 4M3CAODx3hYGuOu1Y7eNi3MN15Q8M0oW5J2JMajQ/hIACQ/2p2BJMWjbUTUJi1jEra cXL1DAoEPUQww== Received: by pali.im (Postfix) id BC1CF7C3; Wed, 27 Jul 2022 17:21:35 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: u-boot@lists.denx.de Subject: [PATCH] board: freescale: p1_p2_rdb_pc: Remove I-flag from second L2 SRAM mapping Date: Wed, 27 Jul 2022 17:21:28 +0200 Message-Id: <20220727152128.26316-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with locked lines. P2020 reference manual about L2 memory-mapping mode says: Accesses to memory-mapped SRAM are cacheable only in the corresponding e500 L1 caches. So there is no need to set Caching-Inhibit I-bit for second part of initial L2 SRAM mapping in TLB entry. Remove it. First part of initial L2 SRAM mapping already does not have I-bit set. For more details see also: https://lore.kernel.org/u-boot/20220508150844.qqxg452rs4wtf5bs@pali/ Signed-off-by: Pali Rohár --- board/freescale/p1_p2_rdb_pc/tlb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 52acd22dc95a..74bf8cc58ff9 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -105,14 +105,14 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* RAMBOOT/SPL */ #ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ + /* ***G - L2SRAM */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #if CONFIG_SYS_L2_SIZE >= (256 << 10) SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 12, BOOKE_PAGESZ_256K, 1) #endif #endif -- 2.20.1