From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A35C4C00144 for ; Mon, 1 Aug 2022 13:32:42 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 51ECC844E4; Mon, 1 Aug 2022 15:32:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="d1t52kaw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EC26F8415B; Mon, 1 Aug 2022 15:32:10 +0200 (CEST) Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0A83184488 for ; Mon, 1 Aug 2022 15:32:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 6FDBCCE16B1; Mon, 1 Aug 2022 13:32:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5F0E2C433B5; Mon, 1 Aug 2022 13:32:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659360722; bh=ABBSkox2IooOL2kBib+zmLiKYcZ+NZDwkfnCx4DpPpQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d1t52kawUNdZgfjaP7UYMRXaHbrlyivmVtqaUsCV8ltUQ6SjsHAOhfojDmr0Iog3c P7Uqfh6gNqtQDh0JNmPc0dWYx9h9e50e850NmyY+cBUaxeEWCinmaO+XpdpuPx+YOG sO8w78rpriblhAx6DHeyKQXyaBC/wr6nQz0sdmrFpznwka533UuAWxfvUeg4zulqQO qaWQIIO6cphffnUI/fnbx7cuIsqNpTSXqZAqDRno2o0VNNyv44ucSCHZ/9iL9ZpDT4 DxMKNJG5iAWEMjr5dsC7kxun8BxHU8fj0961UwPvwZeqcz2qDFgK5YBMe++K029gia 5FhQmfR69Bh2w== Received: by pali.im (Postfix) id 6E66475F; Mon, 1 Aug 2022 15:31:59 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: "Peng Fan (OSS)" Cc: Tom Rini , u-boot@lists.denx.de Subject: [PATCH v2 1/4] board: freescale: p1_p2_rdb_pc: Add workaround for board reset reboot loop Date: Mon, 1 Aug 2022 15:31:43 +0200 Message-Id: <20220801133146.11481-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220501122314.32626-1-pali@kernel.org> References: <20220501122314.32626-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean CPLD's system reset register on P1/P2 RDB boards is not autocleared after flipping it. If this register is set to one in 100ms after reset starts then CPLD triggers another CPU reset. This means that trying to reset board via CPLD system reset register cause reboot loop. To prevent this reboot loop, the only workaround is to try to clear CPLD's system reset register as early as possible. U-Boot is already doing it in its board_early_init_f() function, which seems to be enough as register is cleared prior CPLD triggers another reset. But board_early_init_f() is not called from SPL and therefore usage of SPL can cause reboot loop. To prevent reboot loop when using SPL, call board_early_init_f() function in SPL too. For accessing CPLD memory space it is needed to have CPLD entry in TLB. With this change it is possible to trigger board reset via CPLD's system reset register on P2020 RDB board. Signed-off-by: Pali Rohár --- Changes in v2: * Resend patch * Update comment about watchdog --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 13 +++++++++++++ board/freescale/p1_p2_rdb_pc/spl.c | 6 ++++++ board/freescale/p1_p2_rdb_pc/tlb.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 343059c09c36..84e1d65cdb1f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -97,6 +97,19 @@ void board_cpld_init(void) out_8(&cpld_data->status_led, CPLD_STATUS_LED); out_8(&cpld_data->fxo_led, CPLD_FXO_LED); out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * CPLD does not trigger reset of CPU for 100ms after the last reset. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible + * and it has to be done in 100ms since the last start of reset. + */ out_8(&cpld_data->system_rst, CPLD_SYS_RST); } diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 22156f2824ec..def28665960d 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -31,6 +31,12 @@ void board_init_f(ulong bootflag) u32 plat_ratio, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + console_init_f(); /* Set pmuxcr to allow both i2c1 and i2c2 */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 13f3a1edf68d..2d431d6d0d90 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -61,11 +61,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif +#endif /* not SPL */ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ -- 2.20.1