From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 066ADC19F2B for ; Thu, 4 Aug 2022 10:42:25 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A084A84826; Thu, 4 Aug 2022 12:42:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Co7TmOeE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9641E84826; Thu, 4 Aug 2022 12:42:20 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5659F84205 for ; Thu, 4 Aug 2022 12:42:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E267CB82511; Thu, 4 Aug 2022 10:42:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4304C433D6; Thu, 4 Aug 2022 10:42:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659609736; bh=QK/oQ6hbgvoWXyJeixuHm3jd6jUpj+4QpMxDzb6WlXc=; h=From:To:Cc:Subject:Date:From; b=Co7TmOeELGeQ1y3K84qHXoDjQHq/0nJeF9be0BAqEUgKJ2lC1M5j50gisbaqhVqE8 TCOJ7cbHQGJfygi5kWVL1hiwA33OJi+IB+ARfFPbakLxkvX8dL3/7Ii9sABqJXh988 VGTJcyKFo9ySP+fsMYDEQUYSe5mHZTbKY+XGQE/NnyrhA4Ff2SGxBDHFGcjkbZcZA8 1VCBHanY8bhWIdyULGx2Ya0fmedEeZgH19IUeDLJd7arhU70ThEZvaTcocXbLIYEHU JtTFvKiMNIPpT78PSScAOmJKMemM7LVhAojyRoin1RHgfygZmuAO2UAoC3LmnQFvVU r3mqZbciaey6Q== Received: by pali.im (Postfix) id A960C80A; Thu, 4 Aug 2022 12:42:12 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese Cc: =?UTF-8?q?Marek=20Beh=C3=BAn?= , u-boot@lists.denx.de Subject: [PATCH u-boot-marvell 1/3] arm64: a37xx: pinctrl: Fix definitions for MPP pins 20-22 Date: Thu, 4 Aug 2022 12:41:54 +0200 Message-Id: <20220804104156.22209-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Signed-off-by: Pali Rohár --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index bb7a76baed1f..a5407a16ee36 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), }; -- 2.20.1