[PATCH 1/4] configs: imx8mn_beacon: Re-align memory to standard imx8mn settings

[PATCH 1/4] configs: imx8mn_beacon: Re-align memory to standard imx8mn settings

[Adam Ford]

The imx8mn_beacon board does not use the same memory map as the reference
design from NXP or other imx8mn boards.  As such, memory is more limited
in SPL.

Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases
the amount of available meory for the SPL stack.  Doing this allows
the board to no longer define CONFIG_MALLOC_F_ADDR.

Since SYS_LOAD_ADDR also does not align with other boards, move it too.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
Depends on

https://patchwork.ozlabs.org/project/uboot/list/?series=312020
https://patchwork.ozlabs.org/project/uboot/list/?series=312016
https://patchwork.ozlabs.org/project/uboot/list/?series=312002


diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index bd17788768..98a75d4950 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -15,10 +15,9 @@ CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SYS_MEMTEST_START=0x40000000
 CONFIG_SYS_MEMTEST_END=0x44000000
 CONFIG_LTO=y
@@ -34,12 +33,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x95e000
+CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_STACK=0x980000
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 738d308f45..271578985f 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -14,10 +14,9 @@ CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SYS_MEMTEST_START=0x40000000
 CONFIG_SYS_MEMTEST_END=0x44000000
 CONFIG_LTO=y
@@ -33,12 +32,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x95e000
+CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_STACK=0x980000
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index ecaefd8930..6da2182eb3 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -14,10 +14,9 @@ CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_BEACON=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SYS_MEMTEST_START=0x40000000
 CONFIG_SYS_MEMTEST_END=0x44000000
 CONFIG_LTO=y
@@ -33,12 +32,12 @@ CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x95e000
+CONFIG_SPL_BSS_START_ADDR=0x950000
 CONFIG_SPL_BSS_MAX_SIZE=0x2000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK=0x187ff0
+CONFIG_SPL_STACK=0x980000
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 6faecbde77..930b11b75e 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -13,14 +13,6 @@
 #define CONFIG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
-#ifdef CONFIG_SPL_BUILD
-/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
-#define CONFIG_MALLOC_F_ADDR		0x184000
-
-/* For RAW image gives a error info not panic */
-
-#endif /* CONFIG_SPL_BUILD */
-
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"script=boot.scr\0" \
-- 
2.34.1

[PATCH 2/4] regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled

[Adam Ford]

If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
driver throws a compile error.  Fix this by putting the function
to bind children into an if-statement checking for PMIC_CHILDREN.

Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
still permits some read/write functions to access the PMIC in
early startup.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c
index cb9238972f..fdbbd6f559 100644
--- a/drivers/power/pmic/bd71837.c
+++ b/drivers/power/pmic/bd71837.c
@@ -63,10 +63,11 @@ static int bd71837_bind(struct udevice *dev)
 
 	debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
 
-	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
-	if (!children)
-		debug("%s: %s - no child found\n", __func__, dev->name);
-
+	if (CONFIG_IS_ENABLED(PMIC_CHILDREN)) {
+		children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+		if (!children)
+			debug("%s: %s - no child found\n", __func__, dev->name);
+	}
 	/* Always return success for this device */
 	return 0;
 }
-- 
2.34.1

[PATCH 3/4] configs: imx8mn_beacon: Enable SPL_DM_PMIC_BD71837

[Adam Ford]

To properly operate the Nano with LPDDR4 at 1.6GHz, the
voltage needs to be adjusted before DDR is initialized.
Enable the PMIC in SPL to do this.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 98a75d4950..fda545a9ad 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -121,6 +121,7 @@ CONFIG_PINCTRL_IMX8M=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_BD71837=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 271578985f..0ffcbcb475 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -125,6 +125,7 @@ CONFIG_PINCTRL_IMX8M=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_BD71837=y
 CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index 6da2182eb3..94d069cbfa 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -125,6 +125,7 @@ CONFIG_PINCTRL_IMX8M=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_BD71837=y
 CONFIG_DM_REGULATOR_FIXED=y
-- 
2.34.1

[PATCH 4/4] imx: imx8mn-beacon: Configure PMIC before DDR initialization

[Adam Ford]

The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit or it will be running out of
spec.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index 029f71bc99..9acd916180 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -74,6 +74,38 @@ static iomux_v3_cfg_t const pwm_pads[] = {
 	IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
 };
 
+static int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@4b", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic\n");
+		return 0;
+	}
+
+	if (ret != 0)
+		return ret;
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+	/* lock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+
 int board_early_init_f(void)
 {
 	/* Claiming pwm pins prevents LCD flicker during startup*/
@@ -107,6 +139,9 @@ void board_init_f(ulong dummy)
 
 	enable_tzc380();
 
+	/* LPDDR4 at 1.6GHz requires a voltage adjustment on the PMIC */
+	power_init_board();
+
 	/* DDR initialization */
 	spl_dram_init();
 
-- 
2.34.1

Re: [PATCH 2/4] regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled

[Simon Glass]

On Wed, 17 Aug 2022 at 05:24, Adam Ford <aford173@gmail.com> wrote:
>
> If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
> driver throws a compile error.  Fix this by putting the function
> to bind children into an if-statement checking for PMIC_CHILDREN.
>
> Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
> still permits some read/write functions to access the PMIC in
> early startup.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Simon Glass <sjg@chromium.org>