From: Jit Loon Lim <jit.loon.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>,
Vignesh R <vigneshr@ti.com>, Marek <marex@denx.de>,
Simon <simon.k.r.goldschmidt@gmail.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Siew Chin <elly.siew.chin.lim@intel.com>,
Sin Hui <sin.hui.kho@intel.com>, Raaj <raaj.lokanathan@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Chee Hong Ang <chee.hong.ang@intel.com>
Subject: [PATCH] arm: socfpga: stratix10: Enable CONFIG_FPGA_INTEL_PR
Date: Thu, 1 Sep 2022 13:26:23 +0800 [thread overview]
Message-ID: <20220901052623.21110-1-jit.loon.lim@intel.com> (raw)
From: Chee Hong Ang <chee.hong.ang@intel.com>
Enable Intel FPGA Partial Reconfiguration driver by
default for Stratix10.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
configs/socfpga_stratix10_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 07e9f20a41..8bc41cb289 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -66,6 +66,7 @@ CONFIG_BOOTFILE="Image"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
--
2.26.2
reply other threads:[~2022-09-01 5:26 UTC|newest]
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