[PATCH 0/2] *** SUBJECT HERE ***

[PATCH 0/2] *** SUBJECT HERE ***

[sieu.mun.tang]

From: Sieu Mun Tang <sieu.mun.tang@intel.com>

*** BLURB HERE ***

Tien Fong Chee (2):
  arch: arm: mach-socfpga: Use custom header target buffer in SPL
  arch: arm: mach-socfpga: Add SPL fitImage config match

 arch/arm/mach-socfpga/spl_a10.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

-- 
2.25.1

[PATCH 1/2] arch: arm: mach-socfpga: Use custom header target buffer in SPL

[sieu.mun.tang]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Allocate buffer from bottom half of DDR for the image headers in SPL on
Arria10. This allows SPL to load the fitImage header, parse it,
extract the FPGA core bitstream section from it, and program the FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
---
 arch/arm/mach-socfpga/spl_a10.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index ec67a5b0eb..bfcbd1dfe1 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -28,6 +28,8 @@
 #include <watchdog.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/fpga_manager.h>
+#include <exports.h>
+#include <log.h>
 #include <mmc.h>
 #include <memalign.h>
 #include <linux/delay.h>
@@ -281,3 +283,13 @@ void spl_board_prepare_for_boot(void)
 	writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
 	       SYSMGR_A10_ROMCODE_INITSWSTATE);
 }
+
+#if defined(CONFIG_SPL_LOAD_FIT) && defined(CONFIG_SPL_SPI_LOAD)
+struct image_header *spl_get_load_buffer(int offset, size_t size)
+{
+	if (gd->ram_size)
+		return (struct image_header *)(gd->ram_size / 2);
+	else
+		return NULL;
+}
+#endif
-- 
2.25.1

[PATCH 2/2] arch: arm: mach-socfpga: Add SPL fitImage config match

[sieu.mun.tang]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add empty SPL fitImage configuration match. This can be extended
if there is ever need to support multiple boards with single SFP
image.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
---
 arch/arm/mach-socfpga/spl_a10.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index bfcbd1dfe1..64f801dfe5 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -292,4 +292,12 @@ struct image_header *spl_get_load_buffer(int offset, size_t size)
 	else
 		return NULL;
 }
+
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
 #endif
-- 
2.25.1

[PATCH 0/2] *** SUBJECT HERE ***

[Jit Loon Lim]

*** BLURB HERE ***

Chee Hong Ang (2):
  arm: socfpga: soc64: Enable L2 reset on S10
  arm: socfpga: soc64: Perform warm reset after L2 reset in SPL on S10

 .../include/mach/reset_manager_soc64.h        |  1 +
 arch/arm/mach-socfpga/lowlevel_init_soc64.S   | 24 ++++++++
 drivers/sysreset/sysreset_socfpga_soc64.c     | 58 ++++++++++++++++++-
 include/configs/socfpga_soc64_common.h        |  7 +++
 4 files changed, 88 insertions(+), 2 deletions(-)

-- 
2.26.2