From: Jit Loon Lim <jit.loon.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>,
Vignesh R <vigneshr@ti.com>, Marek <marex@denx.de>,
Simon <simon.k.r.goldschmidt@gmail.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Siew Chin <elly.siew.chin.lim@intel.com>,
Sin Hui <sin.hui.kho@intel.com>, Raaj <raaj.lokanathan@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>
Subject: [PATCH] arm: Enable cache-pl310 driver build for both SPL and proper U-Boot
Date: Mon, 5 Sep 2022 20:55:11 +0800 [thread overview]
Message-ID: <20220905125511.14495-1-jit.loon.lim@intel.com> (raw)
From: Tien Fong Chee <tien.fong.chee@intel.com>
Moved CONFIG_SYS_L2_PL310 to the location where the build on the
cache-pl310 can be taken in both SPL and proper U-Boot. This driver is
required for SoCFPGA when temporarily turning on the cache for better
performance in initializing whole DDR to zero.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/lib/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c603fe61bc..575042e6df 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,6 +43,7 @@ ifdef CONFIG_ARM64
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o
else
+obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
endif
--
2.26.2
reply other threads:[~2022-09-05 12:55 UTC|newest]
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