From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18C05C54EE9 for ; Thu, 8 Sep 2022 14:07:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0052084B22; Thu, 8 Sep 2022 16:07:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="Uoa09eHF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 361E584B07; Thu, 8 Sep 2022 16:07:05 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2C7A884B0E for ; Thu, 8 Sep 2022 16:07:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kabel@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D24F4B820FF; Thu, 8 Sep 2022 14:07:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83E79C4347C; Thu, 8 Sep 2022 14:06:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662646020; bh=mdhgIxhCHEeeY/u0YApUJ64qpZVeAYvZD1X6gf7UtjM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Uoa09eHFpu0jdPSpXZOUfiWcxq4r2FnezThDZVgny8KfoaTiG+Is3CYqPjc587ule ftqvN7PV5FARCu+WTiREsEnqzWNPqrn+Lw6F9jnx60Rabx67HFCR0CChHVqS5sMvAD kPv5ocBq8hKsQJE5BjHvdRrbCF3zQEVs7znfgT+7o3GhnwmfcHZgnxr2AcfkrgM2D1 QUPdI1raePYOx8ZtZYEyOs7jHb3qbJjm6a1XNX2JEGqroHmStg3vn6KfkO5lfDZ1Zh xraSCQoJz29YH0qxR7zNRO3VFY+zzlr6w/mJPA0bdIOqS5jdM8XlEVzZfj40+A5xj5 U2ZKm38i/Xzyg== From: =?UTF-8?q?Marek=20Beh=C3=BAn?= To: Stefan Roese Cc: pali@kernel.org, U-Boot Mailing List , =?UTF-8?q?Marek=20Beh=C3=BAn?= Subject: [PATCH u-boot-marvell 2/5] arm: mvebu: Guard non-AXP code by checking for AXP Date: Thu, 8 Sep 2022 16:06:51 +0200 Message-Id: <20220908140654.7051-3-kabel@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220908140654.7051-1-kabel@kernel.org> References: <20220908140654.7051-1-kabel@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Pali Rohár Commit c86d53fd88df ("arm: mvebu: Don't disable cache at startup on Armada XP at all") introduced branch for non-AXP code which was guarded by A38X condition. Fix this issue by checking for AXP platform, not by A38X. Fixes: c86d53fd88df ("arm: mvebu: Don't disable cache at startup on Armada XP at all") Signed-off-by: Pali Rohár Signed-off-by: Marek Behún --- arch/arm/mach-mvebu/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index b512ccc501..8e5d1ba21e 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -448,7 +448,7 @@ int arch_cpu_init(void) struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - if (IS_ENABLED(CONFIG_ARMADA_38X)) { + if (!IS_ENABLED(CONFIG_ARMADA_XP)) { /* * To fully release / unlock this area from cache, we need * to flush all caches and disable the L2 cache. -- 2.35.1