[PATCH 6/7] arm: mvebu: Add RD-AC5X board

Chris Packham
2022-09-16T04:55:45Z

The RD-AC5X-32G16HVG6HLG-A0 development board main components and features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host port (shared with PCIe)
Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ Port 48
(Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

arch/arm/dts/Makefile | 3 +-
arch/arm/dts/ac5-98dx35xx-rd.dts | 155 +++++++++++++++++++++
arch/arm/mach-mvebu/Kconfig | 9 +-
board/Marvell/mvebu_alleycat-5/MAINTAINERS | 6 +
board/Marvell/mvebu_alleycat-5/Makefile | 3 +
board/Marvell/mvebu_alleycat-5/board.c | 35 +++++
configs/mvebu_ac5_rd_defconfig | 89 ++++++++++++
include/configs/mvebu_alleycat-5.h | 92 ++++++++++++
8 files changed, 390 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
create mode 100644 configs/mvebu_ac5_rd_defconfig
create mode 100644 include/configs/mvebu_alleycat-5.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7330121dba..a334596ada 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9132-db-A.dtb \
cn9132-db-B.dtb \
cn9130-crb-A.dtb \
- cn9130-crb-B.dtb
+ cn9130-crb-B.dtb \
+ ac5-98dx35xx-rd.dtb
endif

dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
new file mode 100644
index 0000000000..94eadd6f71
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For RD-AC5X.
+ *
+ * Copyright (C) 2021 Marvell
+ * Copyright (C) 2022 Allied Telesis Labs
+ */
+/*
+ * Device Tree file for Marvell Alleycat 5X development board
+ * This board file supports the B configuration of the board
+ */
+
+/dts-v1/;
+
+#include "ac5-98dx35xx.dtsi"
+
+/ {
+ model = "Marvell RD-AC5X Board";
+ compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
+
+ aliases {
+ serial0 = &uart0;
+ spiflash0 = &spiflash0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ ethernet0 = &eth0;
+ ethernet1 = &eth1;
+ spi0 = &spi0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ pinctrl0 = &pinctrl0;
+ sar-reg0 = "/config-space/sar-reg";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x2 0x00000000 0x0 0x40000000>;
+ };
+
+ usb1phy: usb-phy {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ config-space {
+ sar-reg {
+ reg = <0x944F8204 0x1>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&eth0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+};
+
+/* USB0 is a host USB */
+&usb0 {
+ status = "okay";
+};
+
+/* USB1 is a peripheral USB */
+&usb1 {
+ status = "okay";
+ phys = <&usb1phy>;
+ phy-names = "usb-phy";
+ dr_mode = "peripheral";
+};
+
+&spi0 {
+ status = "okay";
+
+ spiflash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+ spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "spi_flash_part0";
+ reg = <0x0 0x800000>;
+ };
+
+ parition@1 {
+ label = "spi_flash_part1";
+ reg = <0x800000 0x700000>;
+ };
+
+ parition@2 {
+ label = "spi_flash_part2";
+ reg = <0xF00000 0x100000>;
+ };
+ };
+};
+
+&pinctrl0 {
+ /*
+ * MPP Bus: MPP# mode#
+ * eMMC [0-11] 0x1
+ * SPI[0] [12-17] 0x1
+ * TSEN_INT [18] 0x1
+ * DEV_INIT [19] 0x1
+ * SPI[1] [20-23] 0x3
+ * UART[1] [24-25] 0x3
+ * I2C[0] [26-27] 0x1
+ * XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem
+ * SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem
+ * UART[0] [32-33] 0x1
+ * OOB_SMI [34-35] 0x1
+ * PTP_CLK0_OUT [36] 0x1
+ * PTP_PULSE_OUT [37] 0x1
+ * RCVR_CLK_OUT [38] 0x1
+ * GPIO(in/out) [39] 0x0
+ * GPIO(in/out) [40] 0x0
+ * PTP_REF_CLK [41] 0x1
+ * PTP_CLK0 [42] 0x1
+ * LED0_CLK [43] 0x1
+ * LED0_STB [44] 0x1
+ * LED0_DATA [45] 0x1
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 1 1 1 1 1 1 1 1 1
+ 3 3 3 3 3 3 1 1 1 1
+ 2 2 1 1 1 1 1 1 1 0
+ 0 1 1 1 1 1 >;
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 400a308985..d27c45d58f 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -98,7 +98,7 @@ config CUSTOMER_BOARD_SUPPORT
bool

choice
- prompt "Armada XP/375/38x/3700/7K/8K board select"
+ prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
optional

config TARGET_CLEARFOG
@@ -150,6 +150,10 @@ config TARGET_MVEBU_ARMADA_8K
select BOARD_LATE_INIT
imply SCSI

+config TARGET_MVEBU_ALLEYCAT5
+ bool "Support AlleyCat 5 platforms"
+ select ALLEYCAT_5
+
config TARGET_OCTEONTX2_CN913x
bool "Support CN913x platforms"
select ARMADA_8K
@@ -258,6 +262,7 @@ config SYS_BOARD
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
+ default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5

config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
@@ -278,6 +283,7 @@ config SYS_CONFIG_NAME
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
+ default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5

config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
@@ -297,6 +303,7 @@ config SYS_VENDOR
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
default "mikrotik" if TARGET_CRS3XX_98DX3236
+ default "Marvell" if TARGET_MVEBU_ALLEYCAT5

config SYS_SOC
default "mvebu"
diff --git a/board/Marvell/mvebu_alleycat-5/MAINTAINERS b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
new file mode 100644
index 0000000000..480c07c5f0
--- /dev/null
+++ b/board/Marvell/mvebu_alleycat-5/MAINTAINERS
@@ -0,0 +1,6 @@
+RD-AC5X BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/Marvell/mvebu_alleycat-5/
+F: include/configs/mvebu_alleycat-5.h
+F: configs/mvebu_ac5_rd_defconfig
diff --git a/board/Marvell/mvebu_alleycat-5/Makefile b/board/Marvell/mvebu_alleycat-5/Makefile
new file mode 100644
index 0000000000..29254b4d64
--- /dev/null
+++ b/board/Marvell/mvebu_alleycat-5/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := board.o
diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c
new file mode 100644
index 0000000000..3303d3c2c9
--- /dev/null
+++ b/board/Marvell/mvebu_alleycat-5/board.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int soc_early_init_f(void)
+{
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ soc_early_init_f();
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig
new file mode 100644
index 0000000000..bfc0cd6ba9
--- /dev/null
+++ b/configs/mvebu_ac5_rd_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x200000000
+CONFIG_SYS_MALLOC_LEN=0x900000
+CONFIG_TARGET_MVEBU_ALLEYCAT5=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0x7f012000
+CONFIG_DEBUG_UART_CLOCK=325000000
+CONFIG_SYS_LOAD_ADDR=0x202000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_MEMTEST_START=0x200800000
+CONFIG_SYS_MEMTEST_END=0x200ffffff
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x200FF0000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+CONFIG_BOOTCOMMAND="run get_images; run set_bootargs; booti $kernel_addr $ramfs_addr $fdt_addr"
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_UBI=y
+CONFIG_MAC_PARTITION=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_MVEBU=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MVEBU_SAR=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_E1000=y
+CONFIG_MVNETA=y
+CONFIG_MVMDIO=y
+CONFIG_PCI=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_MVEBU_A3700_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h
new file mode 100644
index 0000000000..a9dbbf1858
--- /dev/null
+++ b/include/configs/mvebu_alleycat-5.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marvell International Ltd
+ */
+
+#ifndef _CONFIG_MVEBU_ALLEYCAY_5_H
+#define _CONFIG_MVEBU_ALLEYCAY_5_H
+
+#include <asm/arch/soc.h>
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x200000000
+
+/* auto boot */
+#define CONFIG_PREBOOT
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
+ 115200, 230400, 460800, 921600 }
+
+/* Default Env vars */
+#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */
+#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 0.0.0.0
+#define CONFIG_ETHPRIME "eth0"
+#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_EXTRA_ENV_SETTINGS "bootcmd=run get_images; " \
+ "run set_bootargs; " \
+ "booti $kernel_addr_r " \
+ "$ramdisk_addr_r " \
+ "$fdt_addr_r\0" \
+ "extra_params=pci=pcie_bus_safe\0" \
+ "kernel_addr_r=0x202000000\0" \
+ "initrd_addr=0x206000000\0" \
+ "initrd_size=0x2000000\0" \
+ "fdt_addr_r=0x201000000\0" \
+ "loadaddr=0x202000000\0" \
+ "hostname=marvell\0" \
+ "ramdisk_addr_r=0x206000000\0" \
+ "ramfs_name=-\0" \
+ "cpuidle=cpuidle.off=1\0" \
+ "fdt_name=fdt.dtb\0" \
+ "netdev=eth0\0" \
+ "ethaddr=00:51:82:11:22:00\0" \
+ "eth1addr=00:51:82:11:22:01\0" \
+ "image_name=Image\0" \
+ "get_ramfs=if test \"${ramfs_name}\"" \
+ " != \"-\"; then setenv " \
+ "ramdisk_addr_r 0x8000000; " \
+ "tftpboot $ramdisk_addr_r " \
+ "$ramfs_name; else setenv " \
+ "ramdisk_addr_r -;fi\0" \
+ "get_images=tftpboot $kernel_addr_r " \
+ "$image_name; tftpboot " \
+ "$fdt_addr_r $fdt_name; " \
+ "run get_ramfs\0" \
+ "console=" "console=ttyS0,115200 "\
+ "earlycon=uart8250,mmio32,0xf0512000\0"\
+ "root=root=/dev/nfs rw\0" \
+ "set_bootargs=setenv bootargs $console"\
+ " $root ip=$ipaddr:$serverip:" \
+ "$gatewayip:$netmask:$hostname"\
+ ":$netdev:none nfsroot="\
+ "$serverip:$rootpath,tcp,v3 " \
+ "$extra_params " \
+ "$cpuidle"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SYS_TCLK 325000000
+
+/* tbd #define CONFIG_BOARD_EARLY_INIT_R */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+
+/* MTD support */
+#define CONFIG_MTD_DEVICE
+
+#endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */
--
2.37.3