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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id y22-20020aa78f36000000b0052d200c8040sm13964488pfr.211.2022.09.16.01.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Sep 2022 01:13:15 -0700 (PDT) From: Kautuk Consul To: Rick Chen , Leo , Sean Anderson , Bin Meng , Anup Patel , Heinrich Schuchardt , Simon Glass , Ilias Apalodimas , Alexandru Gagniuc , Philippe Reynes , Rasmus Villemoes , Eugen Hristev , Stefan Roese , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Qu Wenruo , Loic Poulain , Patrick Delaunay Cc: u-boot@lists.denx.de, Kautuk Consul Subject: [PATCH v2 2/3] arch/riscv: add semihosting support for RISC-V Date: Fri, 16 Sep 2022 13:42:32 +0530 Message-Id: <20220916081233.1970135-3-kconsul@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220916081233.1970135-1-kconsul@ventanamicro.com> References: <20220916081233.1970135-1-kconsul@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 16 Sep 2022 14:22:08 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel Signed-off-by: Kautuk Consul --- arch/riscv/Kconfig | 47 ++++++++++++++++++++++++++++ arch/riscv/include/asm/semihosting.h | 11 +++++++ arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 ++ arch/riscv/lib/interrupts.c | 11 +++++++ arch/riscv/lib/semihosting.c | 24 ++++++++++++++ 6 files changed, 96 insertions(+) create mode 100644 arch/riscv/include/asm/semihosting.h create mode 100644 arch/riscv/lib/semihosting.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 78e964db12..b15d9028bd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -371,4 +371,51 @@ config TPL_USE_ARCH_MEMSET endmenu +config SEMIHOSTING + bool "Support RISCV semihosting" + select LIB_SEMIHOSTING + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails" + depends on SEMIHOSTING && RISCV + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + +config SPL_SEMIHOSTING + bool "Support RISCV semihosting in SPL" + depends on SPL + select LIB_SEMIHOSTING + help + Semihosting is a method for a target to communicate with a host + debugger. It uses special instructions which the debugger will trap + on and interpret. This allows U-Boot to read/write files, print to + the console, and execute arbitrary commands on the host system. + + Enabling this option will add support for reading and writing files + on the host system. If you don't have a debugger attached then trying + to do this will likely cause U-Boot to hang. Say 'n' if you are unsure. + +config SPL_SEMIHOSTING_FALLBACK + bool "Recover gracefully when semihosting fails in SPL" + depends on SPL_SEMIHOSTING && RISCV + default y + help + Normally, if U-Boot makes a semihosting call and no debugger is + attached, then it will panic due to a synchronous abort + exception. This config adds an exception handler which will allow + U-Boot to recover. Say 'y' if unsure. + endmenu diff --git a/arch/riscv/include/asm/semihosting.h b/arch/riscv/include/asm/semihosting.h new file mode 100644 index 0000000000..7042821e00 --- /dev/null +++ b/arch/riscv/include/asm/semihosting.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#ifndef __ASM_RISCV_SEMIHOSTING_H +#define __ASM_RISCV_SEMIHOSTING_H + +long smh_trap(int sysnum, void *addr); + +#endif /* __ASM_RISCV_SEMIHOSTING_H */ diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h index e8a94fcb1f..2898a770ee 100644 --- a/arch/riscv/include/asm/spl.h +++ b/arch/riscv/include/asm/spl.h @@ -25,6 +25,7 @@ enum { BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, BOOT_DEVICE_BOOTROM, + BOOT_DEVICE_SMH, BOOT_DEVICE_NONE }; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 06020fcc2a..64e29804c1 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -42,3 +42,5 @@ extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o + +obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 100be2e966..bd7cd772b8 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -17,6 +17,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -149,6 +150,16 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs) /* An UEFI application may have changed gd. Restore U-Boot's gd. */ efi_restore_gd(); + if (cause == CAUSE_BREAKPOINT && + CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) { + /* For semihosting fallback we simply skip the ebreak + * instruction. + */ + disable_semihosting(); + epc += 4; + return epc; + } + is_irq = (cause & MCAUSE_INT); irq = (cause & ~MCAUSE_INT); diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c new file mode 100644 index 0000000000..72ea9521dc --- /dev/null +++ b/arch/riscv/lib/semihosting.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include + +long smh_trap(int sysnum, void *addr) +{ + register int ret asm ("a0") = sysnum; + register void *param0 asm ("a1") = addr; + + asm volatile ("\t.option push\n" + "\t.option norvc\n" + "\tj 1f\n" + "\t.align 4\n" + "\t1: slli zero, zero, 0x1f\n" + "\tebreak\n" + "\tsrai zero, zero, 7\n" + "\t.option pop\n" + : "+r" (ret) : "r" (param0) : "memory"); + + return ret; +} -- 2.34.1