From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6A7DECAAD8 for ; Fri, 16 Sep 2022 12:24:59 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 29E9784BDC; Fri, 16 Sep 2022 14:23:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Ri1aw5zB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 7774D84BA4; Fri, 16 Sep 2022 10:19:50 +0200 (CEST) Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BEBA8849AD for ; Fri, 16 Sep 2022 10:19:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kconsul@ventanamicro.com Received: by mail-pg1-x530.google.com with SMTP id r23so11097853pgr.6 for ; Fri, 16 Sep 2022 01:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=ONzdyX84qtpKXsueDRhZook3p1KyOUb9ZSHELX3GhP8=; b=Ri1aw5zB/OX/xoZcW5FOLzvsgJq81geKFIdfUL05OYI686VIOTZKjk2rEcz5+BoMG2 tcEe7KTQUioAaOM09l9uALHVFJ5Zfom93OvmslMOGhf7nmZ/9MUU3IMz7nAZyumO/xsz xSGQkhCweJmognmS/qQMNo0/idFAsTrkh1oHcEYrlqvRDXGl6MvV33E6G2oAgWBxLwyS 7UMYedgIHoLR7PABlIUYnGOqe+bIqY+O9d9xsarey3DKhdWhJo7hbM4KcXq5ICU69CRz JU6Td/53L+iKYzSZRpOtfJXzb2pVDrWmfQHZsXjReNcXRt79JSN0iHw+Fu6hgZ2e7/xp jdCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=ONzdyX84qtpKXsueDRhZook3p1KyOUb9ZSHELX3GhP8=; b=Jryg2+00uAwPENa3St7pOJLIb6G5wkfJ4VaOpJw2Yl+cZSN6nSgtsa/Zpi3ASpnPCl OqmGJVOsi4IyHkMVCEEtk7/gCgG7M2M4UMEI3FEMz/vXQ1+8rTW9f7E0FECPnvQbfyCV 8rXdi9qaIIc+CFCi3yK0v4nrutvAZDZHflwt2Wwk15iipPL2v0htd2LIh3Hwi112PXGf v2nHlA8YG7E0gzBGtn8cMuHRG6gzOGTU5d5LCh6jRlrkBDO35OpzOU6jkiUwIG961MyR 9uZaIClskH7tCe6pUILDvez5eGTGrnCxLVnahYbzZ680ykSFpqZh9EQ7dwo0DX+J3gHu s53A== X-Gm-Message-State: ACrzQf2+BRd7m9D183qy94Cf57ypr1lgwq0PwO9P/IG00xsNUtO58i6n 9m60p1jyVDNoYuSfmsy4O+F8iQ== X-Google-Smtp-Source: AMsMyM6KZjVgMHOjBxg8Z0PNEcyg5M/5OvJCKgssRNETx92tVo3oZwLUgF3y+kGfxoJpVKYjadymKg== X-Received: by 2002:a63:174c:0:b0:438:aece:e2f5 with SMTP id 12-20020a63174c000000b00438aecee2f5mr3527555pgx.366.1663316386159; Fri, 16 Sep 2022 01:19:46 -0700 (PDT) Received: from performance-PowerEdge-T440.. ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id j9-20020a63e749000000b004393c5a8006sm7058695pgk.75.2022.09.16.01.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Sep 2022 01:19:45 -0700 (PDT) From: Kautuk Consul To: Rick Chen , Leo , Sean Anderson , Bin Meng , Anup Patel , Heinrich Schuchardt , Simon Glass , Ilias Apalodimas , Alexandru Gagniuc , Philippe Reynes , Rasmus Villemoes , Eugen Hristev , Stefan Roese , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Qu Wenruo , Loic Poulain , Patrick Delaunay Cc: u-boot@lists.denx.de, Kautuk Consul Subject: [PATCH v2 0/3] Add riscv semihosting support in u-boot Date: Fri, 16 Sep 2022 13:49:29 +0530 Message-Id: <20220916081929.1975717-1-kconsul@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Fri, 16 Sep 2022 14:22:08 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v1: - Moved the identical smh_* and semihosting_enabled/disable_semihosting code of ARM and RISC-V to lib/semihosting.c - Extend the handle_trap() functionality to call disable_semihosting() if the cause is a breakpoint (i.e. ebreak instruction) - Change our implementation of semihosting_enabled to be exactly the same as the way ARM implemented it - Additionally enable the CONFIG_SPL_FS_EXT4 and CONFIG_SPL_FS_FAT configs for qemu defconfigs so that CONFIG_SPL_FS_LOAD_PAYLOAD_NAME gets automatically enabled instead of us #defining it in include/configs/qemu-riscv.h Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V board: qemu-riscv: enable semihosting arch/arm/Kconfig | 2 + arch/arm/lib/semihosting.c | 179 +------------------------- arch/riscv/Kconfig | 47 +++++++ arch/riscv/include/asm/semihosting.h | 11 ++ arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 11 ++ arch/riscv/lib/semihosting.c | 24 ++++ configs/qemu-riscv32_defconfig | 4 + configs/qemu-riscv32_smode_defconfig | 4 + configs/qemu-riscv32_spl_defconfig | 7 + configs/qemu-riscv64_defconfig | 4 + configs/qemu-riscv64_smode_defconfig | 4 + configs/qemu-riscv64_spl_defconfig | 7 + include/semihosting.h | 11 ++ lib/Kconfig | 3 + lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++ 18 files changed, 331 insertions(+), 178 deletions(-) create mode 100644 arch/riscv/include/asm/semihosting.h create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1