From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4394C54EE9 for ; Fri, 16 Sep 2022 09:12:46 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F3E88849D8; Fri, 16 Sep 2022 11:12:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="IctngReE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4D38184B9B; Fri, 16 Sep 2022 11:12:44 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EE48184970 for ; Fri, 16 Sep 2022 11:12:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 98627B8248D; Fri, 16 Sep 2022 09:12:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9321C433D7; Fri, 16 Sep 2022 09:12:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663319560; bh=bO8m7W9/49cDZzIsWB1sWV7YVG6yOT621MrA84KcbM4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=IctngReE39EQPAlIN8kFjYsL/hOPZ6l3OJadevrfjchwXxv5p1e4TY87rTf302wwl QvOhN59zscb7q8f/FCq2dmIE8O2oN+2eNWqpwYFWk3jwxLymdejaTYa3N/9henN0QL 4bp6bqr1t8/CObXR7INbp4RnqoptpO9UjcdnMd1sYegCw7Gk6r80uMwtSNR1KiYoX6 EOiDXqt7b6oG2ytmsFF7c4SWkubnRkFKx5esIk4ScvrySIAK1iiMwh767YAnaYQyrR ARac5XKKMQP7n7Eo2/a1OhekaLB6zHSypeS/i8vrZ/WJh4hNL30DRR+FFjFpPkdiT6 vLzOBLp0JU6FA== Received: by pali.im (Postfix) id 25E7B7B3; Fri, 16 Sep 2022 11:12:37 +0200 (CEST) Date: Fri, 16 Sep 2022 11:12:37 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Kautuk Consul Cc: u-boot@lists.denx.de Subject: Re: [PATCH v2 0/3] Add riscv semihosting support in u-boot Message-ID: <20220916091237.n5pcuqtzgulcqrf2@pali> References: <20220916081233.1970135-1-kconsul@ventanamicro.com> <20220916090827.maz2lh2eov65tvo3@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean That is strange because I'm not aware of the fact that I'm riscv maintainer. On Friday 16 September 2022 14:40:46 Kautuk Consul wrote: > Sorry about that! > I ran get_maintainer.pl on my patchset and got your name > along with several others so I also sent to you. > > On Fri, Sep 16, 2022 at 2:38 PM Pali Rohár wrote: > > > > Hello! I'm not riscv maintainer and therefore I'm not going to review > > this patch series. Please do not spam me with unrelated emails and > > patches as I would loose track of patches and emails which are import > > and which I should review. Thanks. > > > > On Friday 16 September 2022 13:42:30 Kautuk Consul wrote: > > > Semihosting is a mechanism that enables code running on > > > a target to communicate and use the Input/Output > > > facilities on a host computer that is running a debugger. > > > This patchset adds support for semihosting in u-boot > > > for RISCV64 targets. > > > > > > CHANGES since v1: > > > - Moved the identical smh_* and semihosting_enabled/disable_semihosting > > > code of ARM and RISC-V to lib/semihosting.c > > > - Extend the handle_trap() functionality to call disable_semihosting() > > > if the cause is a breakpoint (i.e. ebreak instruction) > > > - Change our implementation of semihosting_enabled to be exactly the > > > same as the way ARM implemented it > > > - Additionally enable the CONFIG_SPL_FS_EXT4 and CONFIG_SPL_FS_FAT > > > configs for qemu defconfigs so that CONFIG_SPL_FS_LOAD_PAYLOAD_NAME > > > gets automatically enabled instead of us #defining it in > > > include/configs/qemu-riscv.h > > > > > > Compilation and test commands for SPL and S-mode configurations > > > ================================================================= > > > > > > U-Boot S-mode on QEMU virt > > > ---------------------------- > > > // Compilation of S-mode u-boot > > > ARCH=riscv > > > CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > make qemu-riscv64_smode_defconfig > > > make > > > // Run riscv 64-bit u-boot with opensbi on qemu > > > qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ > > > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ > > > u-boot/u-boot.bin > > > > > > U-Boot SPL on QEMU virt > > > ------------------------ > > > // Compilation of u-boot-spl > > > ARCH=riscv > > > CROSS_COMPILE=riscv64-unknown-linux-gnu- > > > make qemu-riscv64_spl_defconfig > > > make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin > > > // Run 64-bit u-boot-spl in qemu > > > qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ > > > u-boot/spl/u-boot-spl.bin -device\ > > > loader,file=u-boot/u-boot.itb,addr=0x80200000 > > > > > > Kautuk Consul (3): > > > lib: Add common semihosting library > > > arch/riscv: add semihosting support for RISC-V > > > board: qemu-riscv: enable semihosting > > > > > > arch/arm/Kconfig | 2 + > > > arch/arm/lib/semihosting.c | 179 +------------------------- > > > arch/riscv/Kconfig | 47 +++++++ > > > arch/riscv/include/asm/semihosting.h | 11 ++ > > > arch/riscv/include/asm/spl.h | 1 + > > > arch/riscv/lib/Makefile | 2 + > > > arch/riscv/lib/interrupts.c | 11 ++ > > > arch/riscv/lib/semihosting.c | 24 ++++ > > > configs/qemu-riscv32_defconfig | 4 + > > > configs/qemu-riscv32_smode_defconfig | 4 + > > > configs/qemu-riscv32_spl_defconfig | 7 + > > > configs/qemu-riscv64_defconfig | 4 + > > > configs/qemu-riscv64_smode_defconfig | 4 + > > > configs/qemu-riscv64_spl_defconfig | 7 + > > > include/semihosting.h | 11 ++ > > > lib/Kconfig | 3 + > > > lib/Makefile | 2 + > > > lib/semihosting.c | 186 +++++++++++++++++++++++++++ > > > 18 files changed, 331 insertions(+), 178 deletions(-) > > > create mode 100644 arch/riscv/include/asm/semihosting.h > > > create mode 100644 arch/riscv/lib/semihosting.c > > > create mode 100644 lib/semihosting.c > > > > > > -- > > > 2.34.1 > > >