From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34C74C54EE9 for ; Fri, 16 Sep 2022 14:24:01 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AFFDF84BC0; Fri, 16 Sep 2022 16:23:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CrWVbrqj"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1B9C984BC6; Fri, 16 Sep 2022 16:23:51 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 79B2C84BAC for ; Fri, 16 Sep 2022 16:23:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663338225; x=1694874225; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MV4a/R83dykOc1rFASlArxvLQgxhwmatHJ1znLgGIRQ=; b=CrWVbrqjNOeF2Q1p6f/qPLE1Ag7m7/joh45ZFP/KUjskSJHl+8MskeMK TRTDSDl/XbJCgGX4+TNrKbr0CseYkdf1lKMNsMBSwYBjSf9NRMAxJ4VLz x9UpIkjRjfycRTHIy45/FURLdBvpnBek5/IAWO1OpSsxBXJcLUWwymb3c mmpFFU0cGLjlmK83Wr7I5O9lcuacIz3AluMwKmRJpNMLssi8nh+K22Pme zKPqP2zSdZT6VSWxpjAZUQZtRfCkuH3XKFEqQ2df/+8gunub8KEQ7ioGx uqWo/zUczG2gQUZpm9pfryM2aJcqcJnJnvWnmXOw7NXi/3pblMga/P43R Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="298993864" X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="298993864" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 07:23:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,320,1654585200"; d="scan'208";a="862752307" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga006.fm.intel.com with ESMTP; 16 Sep 2022 07:23:39 -0700 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id BD1D532F4; Fri, 16 Sep 2022 22:23:38 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id BB37EE00420; Fri, 16 Sep 2022 22:23:38 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , "Ooi, Joyce" , Ooi@ecsmtp.png.intel.com Subject: [PATCH 2/2] arm: spl: create a common spl for Stratix10 and Agilex Date: Fri, 16 Sep 2022 22:23:36 +0800 Message-Id: <20220916142336.18907-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220916142336.18907-1-jit.loon.lim@intel.com> References: <20220916142336.18907-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: "Ooi, Joyce" Since Stratix10 and Agilex are using ARM64, there are some common codes in the SPL. Hence, spl_soc64.c is created to place the common codes. Signed-off-by: Ooi, Joyce Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/spl_s10.c | 63 --------------------------- arch/arm/mach-socfpga/spl_soc64.c | 71 +++++++++++++++++++++++++++++-- 2 files changed, 67 insertions(+), 67 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index c4b82ebf14..fb807acf27 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -29,69 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 spl_boot_device(void) -{ - int ret, size; - ofnode node; - const fdt32_t *phandle_p; - u32 phandle; - struct udevice *dev; - - node = ofnode_path("/chosen"); - if (!ofnode_valid(node)) { - debug("%s: /chosen node was not found.\n", __func__); - goto fallback; - } - - phandle_p = ofnode_get_property(node, "u-boot,boot0", &size); - if (!phandle_p) { - debug("%s: u-boot,boot0 property was not found.\n", - __func__); - goto fallback; - } - - phandle = fdt32_to_cpu(*phandle_p); - - node = ofnode_get_by_phandle(phandle); - - ret = device_get_global_by_ofnode(node, &dev); - if (ret) { - debug("%s: Boot device at not found, error: %d\n", __func__, - ret); - goto fallback; - } - - debug("%s: Found boot device %s\n", __func__, dev->name); - - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MISC: - return BOOT_DEVICE_NAND; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("%s: Booting from device uclass '%s' is not " - "supported\n", __func__, - dev_get_uclass_name(dev)); - } - -fallback: - /* Return default boot device */ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_mmc_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif -} -#endif - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index ba6efc1d86..ea1acaf309 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -4,22 +4,85 @@ * */ +#include +#include +#include #include +#include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { + int ret, size; + ofnode node; + const fdt32_t *phandle_p; + u32 phandle; + struct udevice *dev; + + node = ofnode_path("/chosen"); + if (!ofnode_valid(node)) { + debug("%s: /chosen node was not found.\n", __func__); + goto fallback; + } + + phandle_p = ofnode_get_property(node, "u-boot,boot0", &size); + if (!phandle_p) { + debug("%s: u-boot,boot0 property was not found.\n", + __func__); + goto fallback; + } + + phandle = fdt32_to_cpu(*phandle_p); + + node = ofnode_get_by_phandle(phandle); + + ret = device_get_global_by_ofnode(node, &dev); + if (ret) { + debug("%s: Boot device at not found, error: %d\n", __func__, + ret); + goto fallback; + } + + debug("%s: Found boot device %s\n", __func__, dev->name); + + switch (device_get_uclass_id(dev)) { + case UCLASS_SPI_FLASH: + return BOOT_DEVICE_SPI; + case UCLASS_MISC: + return BOOT_DEVICE_NAND; + case UCLASS_MMC: + return BOOT_DEVICE_MMC1; + default: + debug("%s: Booting from device uclass '%s' is not supported\n", + __func__, dev_get_uclass_name(dev)); + } + +fallback: + /* Return default boot device */ return BOOT_DEVICE_MMC1; } #if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { - if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) - return MMCSD_MODE_FS; - else - return MMCSD_MODE_RAW; +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif } #endif -- 2.26.2