From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0FE0C32771 for ; Sun, 18 Sep 2022 12:18:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 57B9C84BE6; Sun, 18 Sep 2022 14:18:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iDayiTxX"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id C1F8384BE5; Sun, 18 Sep 2022 14:18:07 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C89BE84A8E for ; Sun, 18 Sep 2022 14:18:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663503482; x=1695039482; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T3z0HOrPzLSwuSVQF+CoZc8LFr87oDmED3gUSLyqRek=; b=iDayiTxXF5S+kQjJZ3tVvbrJeSRVP7JeDvQQwPB2ZXuJOPUgF8vkrFEl p0NrnpsbA5z9SEWmhCuNBCURwalRHhFPaG0FcfS2X6hszcs5L0hfCIeS2 qyAj1efRoxIAH/YXX/IiU8DRzbCfn9tdEY+o1HGPvyxhfLCaaWVHSZdF+ oeCZfadjRLRM8kkgqj0YgULcZlnjKMAdB3xxNshgN2014YzEAe4j2xDKX miKo7zGb94CTdyUXlsfrWmGM9kA8aKhYtrm3gTHbYiLpU2LiUMeKJJsHS lOMCAj3NQfm+dl5dPfpsB1lsBLEhVUorpplJBTm1cvBOoYpRtqUFftE9/ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10473"; a="360967980" X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="360967980" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 05:17:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="648812174" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga008.jf.intel.com with ESMTP; 18 Sep 2022 05:17:55 -0700 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id ECCD732F1; Sun, 18 Sep 2022 20:17:54 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id EBC21E00414; Sun, 18 Sep 2022 20:17:54 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH 3/9] arm: socfpga: dm: Add clock manager for Diamond Mesa Date: Sun, 18 Sep 2022 20:17:45 +0800 Message-Id: <20220918121751.26370-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220918121751.26370-1-jit.loon.lim@intel.com> References: <20220918121751.26370-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Siew Chin Lim Add clock manager driver for Diamond Mesa. Signed-off-by: Siew Chin Lim Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/clock_manager_dm.c | 79 +++++++++++++++++++ .../include/mach/clock_manager_dm.h | 14 ++++ 2 files changed, 93 insertions(+) create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_dm.h diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c b/arch/arm/mach-socfpga/clock_manager_dm.c new file mode 100644 index 0000000000..47a7693845 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_dm.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(socfpga_dm_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(DM_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(DM_L4_SYS_FREE_CLK); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(DM_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(DM_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h new file mode 100644 index 0000000000..a355fda692 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Intel Corporation + */ + +#ifndef _CLOCK_MANAGER_DM_ +#define _CLOCK_MANAGER_DM_ + +unsigned long cm_get_mpu_clk_hz(void); + +#include +#include "../../../../../drivers/clk/altera/clk-dm.h" + +#endif /* _CLOCK_MANAGER_DM_ */ -- 2.26.2