From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4233C54EE9 for ; Sun, 18 Sep 2022 15:13:20 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CE79D84BEA; Sun, 18 Sep 2022 17:13:10 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="brDpreqC"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D958384BE4; Sun, 18 Sep 2022 17:13:07 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7034A84BEA for ; Sun, 18 Sep 2022 17:13:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663513984; x=1695049984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0BUPO6YHwBvZH8gBKe9b+Qm5HFZkw8OAEboB3lIKZmA=; b=brDpreqCPOH3bXoHAHbw0HvUjiYYxS24+Qhf3lyprm5ky5d5M7aL37rR 28VMJ/BPy3XnXz7/CA7sUqejArwNCuNeMcwZO54treffKB8uNkSMEbR6i EHtu+A5XPPt5lUHAV2FVbWVQd/r/xgV+YmavvonPZGL8ax0n6f/sfZKeG jObMmM566EllG3418WbuILvxZnn/8jh6o1Q6N1oSZ3Yc5J0+YzX/kxdUu zoPA4vmIWPbFlFFKYfJm877874TBCr1OClowQvBXy6GxgOXmz9oClCRfB Ox9/mkaOrpXhpXtx/0ncCbNf0rLhqRtHL8Hi0u8023DuK+TtkjWyLORFp w==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="297970687" X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="297970687" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 08:13:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="618207676" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga002.jf.intel.com with ESMTP; 18 Sep 2022 08:12:58 -0700 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 8C5F832F1; Sun, 18 Sep 2022 23:12:57 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 8AB2CE00414; Sun, 18 Sep 2022 23:12:57 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 3/5] arm: socfpga: soc64: Move socfpga_init_smmu() to before boot SSBL Date: Sun, 18 Sep 2022 23:12:51 +0800 Message-Id: <20220918151253.27301-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220918151253.27301-1-jit.loon.lim@intel.com> References: <20220918151253.27301-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan socfpga_init_smmu() change the L3 masters (eg: SDMMC, NAND and etc) to non-secure , this cause the failure when L3 masters loading SSBL image to secure region in DDR. Move socfpga_init_smmu() to spl_perform_fixups(), so, it is called prior running SSBL. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/spl_agilex.c | 1 + .../mach-socfpga/{spl_agilex.c => spl_dm.c} | 38 +++++++------------ arch/arm/mach-socfpga/spl_soc64.c | 3 ++ 3 files changed, 18 insertions(+), 24 deletions(-) copy arch/arm/mach-socfpga/{spl_agilex.c => spl_dm.c} (82%) diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index ee5a9dc1e2..f137b71e99 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -65,6 +65,7 @@ void board_init_f(ulong dummy) cm_print_clock_quick_summary(); firewall_setup(); + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_dm.c similarity index 82% copy from arch/arm/mach-socfpga/spl_agilex.c copy to arch/arm/mach-socfpga/spl_dm.c index ee5a9dc1e2..17b3cb28dc 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_dm.c @@ -1,87 +1,77 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2020 Intel Corporation * */ - -#include -#include -#include #include #include #include #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include - DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; struct udevice *dev; - ret = spl_early_init(); if (ret) hang(); - socfpga_get_managers_addr(); - /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); - #ifdef CONFIG_HW_WATCHDOG /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); hw_watchdog_init(); #endif - /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR); - timer_init(); - sysmgr_pinmux_init(); - + preloader_console_init(); ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { - debug("Clock init failed: %d\n", ret); + printf("Clock init failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CLK, 1, &dev); + if (ret) { + printf("Memory clock init failed: %d\n", ret); hang(); } - - preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary(); firewall_setup(); + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { - debug("CCU init failed: %d\n", ret); + printf("CCU init failed: %d\n", ret); hang(); } - #if CONFIG_IS_ENABLED(ALTERA_SDRAM) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { - debug("DRAM init failed: %d\n", ret); + printf("DRAM init failed: %d\n", ret); hang(); } #endif - mbox_init(); - #ifdef CONFIG_CADENCE_QSPI mbox_qspi_open(); #endif -} +} \ No newline at end of file diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 2204703853..2f0ad65c18 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -27,5 +27,8 @@ u32 spl_boot_mode(const u32 boot_device) /* board specific function prior loading SSBL / U-Boot */ void spl_perform_fixups(struct spl_image_info *spl_image) { + /* Setup and Initialize SMMU */ + socfpga_init_smmu(); + mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); } -- 2.26.2