From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 815E5C6FA82 for ; Thu, 22 Sep 2022 11:44:20 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 15DAA84CF3; Thu, 22 Sep 2022 13:44:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="ucTysGfE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3CD3784CD2; Thu, 22 Sep 2022 13:44:06 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0BAE884CE6 for ; Thu, 22 Sep 2022 13:44:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 97058B83601; Thu, 22 Sep 2022 11:44:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F9A8C433D7; Thu, 22 Sep 2022 11:44:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1663847040; bh=yeJtjW59DOTR+qonYN6j0rsPADxq+MJcp60RdP8SRRk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ucTysGfEjxKFgdI48M1DQ7e+B30SJ3n2/Yg/ms0D1P4dfgPf6s3YNxwjapAkdyvkJ 5sFoQuKCL7Ry2Br1on8HYnxZmH7v2EWmh57ZnXfsqq2XFoxXrpLuc0PYVFkiSJJriW lxkSrCkQgce7JyXmjh0lLbwihYZaGyas6qcF1zcoFyS2TwKEJ/1x9x376uyqTAZXxo jJUDQGLZofxnxhcMhomJn90ilAAtFg+8hXM9vmP+ECX3q+q260V5PttAERiOjPVO6P WCIMVSpPfupFE4vudWO849KkABMEMWDrvJubkexf9SkIe9hI2ee7VLQ3LRsy1Fsny3 VVMYHGNcNg8mg== Received: by pali.im (Postfix) id 4A1D6DEA; Thu, 22 Sep 2022 13:43:57 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Stefan Roese , =?UTF-8?q?Marek=20Beh=C3=BAn?= Cc: u-boot@lists.denx.de Subject: [PATCH 1/3] arm: mvebu: Add support for programming LD0 and LD1 eFuse Date: Thu, 22 Sep 2022 13:43:44 +0200 Message-Id: <20220922114346.25495-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220922114346.25495-1-pali@kernel.org> References: <20220922114346.25495-1-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This patch implements LD eFuse programming support. Armada 385 contains two LD eFuse lines, each is 256 bit long with one additional lock bit. LD 0 line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. U-Boot 32-bit fuse words 0-8 are mapped to LD eFuse line bits 0-255. U-Boot fuse word 9 is mapped to LD eFuse line lock bit. So to program LD 1 General Purpose Data line, use U-Boot fuse command: => fuse prog -y 65 0 0x76543210 => fuse prog -y 65 1 0xfedcba98 => fuse prog -y 65 2 0x76543210 => fuse prog -y 65 3 0xfedcba98 => fuse prog -y 65 4 0x76543210 => fuse prog -y 65 5 0xfedcba98 => fuse prog -y 65 6 0x76543210 => fuse prog -y 65 7 0xfedcba98 => fuse prog -y 65 8 0x1 Signed-off-by: Pali Rohár --- arch/arm/mach-mvebu/efuse.c | 43 ++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/efuse.h | 4 +++ 2 files changed, 47 insertions(+) diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c index 80318c339eb7..4b0433782171 100644 --- a/arch/arm/mach-mvebu/efuse.c +++ b/arch/arm/mach-mvebu/efuse.c @@ -132,6 +132,46 @@ static int prog_efuse(int nr, struct efuse_val *new_val, u32 mask0, u32 mask1) return res; } +int mvebu_prog_ld_efuse(int ld1, u32 word, u32 val) +{ + int i, res; + u32 line[EFUSE_LD_WORDS]; + + res = mvebu_efuse_init_hw(); + if (res) + return res; + + mvebu_read_ld_efuse(ld1, line); + + /* check if lock bit is already programmed */ + if (line[EFUSE_LD_WORDS - 1]) + return -EPERM; + + /* check if word is valid */ + if (word >= EFUSE_LD_WORDS) + return -EINVAL; + + /* check if there is some bit for programming */ + if (val == (line[word] & val)) + return 0; + + enable_efuse_program(); + + mvebu_read_ld_efuse(ld1, line); + line[word] |= val; + + for (i = 0; i < EFUSE_LD_WORDS; i++) { + writel(line[i], ld_efuses + i); + mdelay(1); + } + + mdelay(5); + + disable_efuse_program(); + + return 0; +} + int mvebu_efuse_init_hw(void) { int ret; @@ -254,6 +294,9 @@ int fuse_prog(u32 bank, u32 word, u32 val) { int res = 0; + if (bank == EFUSE_LD0_LINE || bank == EFUSE_LD1_LINE) + return mvebu_prog_ld_efuse(bank == EFUSE_LD1_LINE, word, val); + /* * NOTE: Fuse line should be written as whole. * So how can we do that with this API? diff --git a/arch/arm/mach-mvebu/include/mach/efuse.h b/arch/arm/mach-mvebu/include/mach/efuse.h index 122e735f2fc7..b125c30beb8c 100644 --- a/arch/arm/mach-mvebu/include/mach/efuse.h +++ b/arch/arm/mach-mvebu/include/mach/efuse.h @@ -70,4 +70,8 @@ int mvebu_write_efuse(int nr, struct efuse_val *val); int mvebu_lock_efuse(int nr); +void mvebu_read_ld_efuse(int ld1, u32 *line); + +int mvebu_prog_ld_efuse(int ld1, u32 word, u32 val); + #endif -- 2.20.1