* [PATCH 1/3] arm: mvebu: Add support for programming LD0 and LD1 eFuse
2022-09-22 11:43 [PATCH 0/3] arm: mvebu: Add support for programming LD eFuse on Armada 385 Pali Rohár
@ 2022-09-22 11:43 ` Pali Rohár
2022-09-22 11:43 ` [PATCH 2/3] arm: mvebu: Add support for specifying VHV_Enable GPIO Pali Rohár
2022-09-22 11:43 ` [PATCH 3/3] arm: mvebu: turris_omnia: Specify VHV gpio for eFUSE programming Pali Rohár
2 siblings, 0 replies; 4+ messages in thread
From: Pali Rohár @ 2022-09-22 11:43 UTC (permalink / raw)
To: Stefan Roese, Marek Behún; +Cc: u-boot
This patch implements LD eFuse programming support. Armada 385 contains two
LD eFuse lines, each is 256 bit long with one additional lock bit. LD 0
line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. U-Boot
32-bit fuse words 0-8 are mapped to LD eFuse line bits 0-255. U-Boot fuse
word 9 is mapped to LD eFuse line lock bit.
So to program LD 1 General Purpose Data line, use U-Boot fuse command:
=> fuse prog -y 65 0 0x76543210
=> fuse prog -y 65 1 0xfedcba98
=> fuse prog -y 65 2 0x76543210
=> fuse prog -y 65 3 0xfedcba98
=> fuse prog -y 65 4 0x76543210
=> fuse prog -y 65 5 0xfedcba98
=> fuse prog -y 65 6 0x76543210
=> fuse prog -y 65 7 0xfedcba98
=> fuse prog -y 65 8 0x1
Signed-off-by: Pali Rohár <pali@kernel.org>
---
arch/arm/mach-mvebu/efuse.c | 43 ++++++++++++++++++++++++
arch/arm/mach-mvebu/include/mach/efuse.h | 4 +++
2 files changed, 47 insertions(+)
diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c
index 80318c339eb7..4b0433782171 100644
--- a/arch/arm/mach-mvebu/efuse.c
+++ b/arch/arm/mach-mvebu/efuse.c
@@ -132,6 +132,46 @@ static int prog_efuse(int nr, struct efuse_val *new_val, u32 mask0, u32 mask1)
return res;
}
+int mvebu_prog_ld_efuse(int ld1, u32 word, u32 val)
+{
+ int i, res;
+ u32 line[EFUSE_LD_WORDS];
+
+ res = mvebu_efuse_init_hw();
+ if (res)
+ return res;
+
+ mvebu_read_ld_efuse(ld1, line);
+
+ /* check if lock bit is already programmed */
+ if (line[EFUSE_LD_WORDS - 1])
+ return -EPERM;
+
+ /* check if word is valid */
+ if (word >= EFUSE_LD_WORDS)
+ return -EINVAL;
+
+ /* check if there is some bit for programming */
+ if (val == (line[word] & val))
+ return 0;
+
+ enable_efuse_program();
+
+ mvebu_read_ld_efuse(ld1, line);
+ line[word] |= val;
+
+ for (i = 0; i < EFUSE_LD_WORDS; i++) {
+ writel(line[i], ld_efuses + i);
+ mdelay(1);
+ }
+
+ mdelay(5);
+
+ disable_efuse_program();
+
+ return 0;
+}
+
int mvebu_efuse_init_hw(void)
{
int ret;
@@ -254,6 +294,9 @@ int fuse_prog(u32 bank, u32 word, u32 val)
{
int res = 0;
+ if (bank == EFUSE_LD0_LINE || bank == EFUSE_LD1_LINE)
+ return mvebu_prog_ld_efuse(bank == EFUSE_LD1_LINE, word, val);
+
/*
* NOTE: Fuse line should be written as whole.
* So how can we do that with this API?
diff --git a/arch/arm/mach-mvebu/include/mach/efuse.h b/arch/arm/mach-mvebu/include/mach/efuse.h
index 122e735f2fc7..b125c30beb8c 100644
--- a/arch/arm/mach-mvebu/include/mach/efuse.h
+++ b/arch/arm/mach-mvebu/include/mach/efuse.h
@@ -70,4 +70,8 @@ int mvebu_write_efuse(int nr, struct efuse_val *val);
int mvebu_lock_efuse(int nr);
+void mvebu_read_ld_efuse(int ld1, u32 *line);
+
+int mvebu_prog_ld_efuse(int ld1, u32 word, u32 val);
+
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/3] arm: mvebu: Add support for specifying VHV_Enable GPIO
2022-09-22 11:43 [PATCH 0/3] arm: mvebu: Add support for programming LD eFuse on Armada 385 Pali Rohár
2022-09-22 11:43 ` [PATCH 1/3] arm: mvebu: Add support for programming LD0 and LD1 eFuse Pali Rohár
@ 2022-09-22 11:43 ` Pali Rohár
2022-09-22 11:43 ` [PATCH 3/3] arm: mvebu: turris_omnia: Specify VHV gpio for eFUSE programming Pali Rohár
2 siblings, 0 replies; 4+ messages in thread
From: Pali Rohár @ 2022-09-22 11:43 UTC (permalink / raw)
To: Stefan Roese, Marek Behún; +Cc: u-boot
VHV_Enable GPIO is required to enable during eFuse programming on Armada
SoCs not from 3700 family. Add support for enabling and disabling VHV pin
via GPIO during eFuse programming, when specified.
All details are in Marvell AN-389: ARMADA VHV Power document
(Doc. No. MV-S302545-00 Rev. C, August 2, 2016).
Note that due to HW Errata 3.6 eFuse erroneous burning (Ref #: HWE-3718342)
VHV power must be disabled while core voltage is off to prevent erroneous
eFuse programming.
This is specified in Marvell ARMADA 380/385/388 Functional Errata,
Guidelines, and Restrictions document
(Doc. No. MV-S501377-00 Rev. D, December 1, 2016).
Signed-off-by: Pali Rohár <pali@kernel.org>
---
arch/arm/mach-mvebu/Kconfig | 15 +++++++++++++
arch/arm/mach-mvebu/efuse.c | 42 ++++++++++++++++++++++++++++++++++---
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index a81b8e2b0df2..d41a0a087bd1 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -347,6 +347,21 @@ config MVEBU_EFUSE_FAKE
from a memory block.
This is can be used for testing prog scripts.
+config MVEBU_EFUSE_VHV_GPIO
+ string "VHV_Enable GPIO name for eFuse programming"
+ depends on MVEBU_EFUSE && !ARMADA_3700
+ help
+ The eFuse programing (burning) phase requires supplying 1.8V to the
+ device on the VHV power pin, while for normal operation the VHV power
+ rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power
+ document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details.
+ .
+ This specify VHV_Enable GPIO name used in U-Boot for enabling VHV power.
+
+config MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW
+ bool "VHV_Enable GPIO is Active Low"
+ depends on MVEBU_EFUSE_VHV_GPIO != ""
+
config SECURED_MODE_IMAGE
bool "Build image for trusted boot"
default false
diff --git a/arch/arm/mach-mvebu/efuse.c b/arch/arm/mach-mvebu/efuse.c
index 4b0433782171..be5dc0e07d9b 100644
--- a/arch/arm/mach-mvebu/efuse.c
+++ b/arch/arm/mach-mvebu/efuse.c
@@ -10,6 +10,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/efuse.h>
#include <asm/arch/soc.h>
+#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/mbus.h>
@@ -56,17 +57,48 @@ static struct mvebu_hd_efuse *get_efuse_line(int nr)
return efuses + nr;
}
-static void enable_efuse_program(void)
+#ifndef DRY_RUN
+static int vhv_gpio;
+#endif
+
+static int enable_efuse_program(void)
{
#ifndef DRY_RUN
+ if (CONFIG_MVEBU_EFUSE_VHV_GPIO[0]) {
+ if (gpio_lookup_name(CONFIG_MVEBU_EFUSE_VHV_GPIO, NULL, NULL, &vhv_gpio)) {
+ printf("Error: VHV gpio lookup failed\n");
+ return -EOPNOTSUPP;
+ }
+ if (gpio_request(vhv_gpio, CONFIG_MVEBU_EFUSE_VHV_GPIO)) {
+ printf("Error: VHV gpio request failed\n");
+ return -EOPNOTSUPP;
+ }
+ if (gpio_direction_output(vhv_gpio,
+ IS_ENABLED(CONFIG_MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW) ? 0 : 1)) {
+ printf("Error: VHV gpio enable failed\n");
+ return -EINVAL;
+ }
+ mdelay(5); /* Wait for the VHV power to stabilize */
+ }
+
setbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_CTRL_PROGRAM_ENABLE);
#endif
+
+ return 0;
}
static void disable_efuse_program(void)
{
#ifndef DRY_RUN
clrbits_le32(MVEBU_EFUSE_CONTROL, MVEBU_EFUSE_CTRL_PROGRAM_ENABLE);
+
+ if (CONFIG_MVEBU_EFUSE_VHV_GPIO[0]) {
+ if (gpio_direction_output(vhv_gpio,
+ IS_ENABLED(CONFIG_MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW) ? 1 : 0))
+ printf("Error: VHV gpio disable failed\n");
+ gpio_free(vhv_gpio);
+ vhv_gpio = 0;
+ }
#endif
}
@@ -123,7 +155,9 @@ static int prog_efuse(int nr, struct efuse_val *new_val, u32 mask0, u32 mask1)
if (!new_val->dwords.d[0] && !new_val->dwords.d[1] && (mask0 | mask1))
return 0;
- enable_efuse_program();
+ res = enable_efuse_program();
+ if (res)
+ return res;
res = do_prog_efuse(efuse, new_val, mask0, mask1);
@@ -155,7 +189,9 @@ int mvebu_prog_ld_efuse(int ld1, u32 word, u32 val)
if (val == (line[word] & val))
return 0;
- enable_efuse_program();
+ res = enable_efuse_program();
+ if (res)
+ return res;
mvebu_read_ld_efuse(ld1, line);
line[word] |= val;
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread