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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id x8-20020a170902a38800b00174ce512262sm5159160pla.182.2022.09.23.00.03.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Sep 2022 00:03:38 -0700 (PDT) From: Kautuk Consul To: Rayagonda Kokatanur , Sean Anderson , Rick Chen , Leo , Bin Meng , Simon Glass , Ilias Apalodimas , Alexandru Gagniuc , Philippe Reynes , Heinrich Schuchardt , Rasmus Villemoes , Eugen Hristev , Stefan Roese , Loic Poulain , Peng Fan , Michal Simek Cc: u-boot@lists.denx.de, Kautuk Consul Subject: [PATCH v5 0/3] Add riscv semihosting support in u-boot Date: Fri, 23 Sep 2022 12:33:17 +0530 Message-Id: <20220923070320.617623-1-kconsul@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v4: - Check arch dependencies for SEMIHOSTING as well as SPL_SEMIHOSTING config options as per Sean's comment. - arch/riscv/lib/interrupts.c: Check for post and pre instructions of the ebreak statement whether they are as per the RISCV semihosting specification. Only then do a disable_semihosting and epc += 4 and return. Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V board: qemu-riscv: enable semihosting arch/arm/Kconfig | 46 ------- arch/arm/lib/semihosting.c | 181 +------------------------- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 25 ++++ arch/riscv/lib/semihosting.c | 24 ++++ configs/qemu-riscv32_defconfig | 4 + configs/qemu-riscv32_smode_defconfig | 4 + configs/qemu-riscv32_spl_defconfig | 7 + configs/qemu-riscv64_defconfig | 4 + configs/qemu-riscv64_smode_defconfig | 4 + configs/qemu-riscv64_spl_defconfig | 7 + include/semihosting.h | 11 ++ lib/Kconfig | 47 +++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++ 16 files changed, 329 insertions(+), 226 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1