From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A6D8C433FE for ; Fri, 7 Oct 2022 17:11:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EFE1F84E8D; Fri, 7 Oct 2022 19:11:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="xKGeWnwZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B864884E7F; Fri, 7 Oct 2022 19:11:23 +0200 (CEST) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6190D80384 for ; Fri, 7 Oct 2022 19:11:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=afd@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 297HBEFZ126971; Fri, 7 Oct 2022 12:11:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1665162674; bh=PSj4F9/YVYX8Nd7F5pZzR8DbVW+iv6pw2It5MhOq8Xg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xKGeWnwZdGUQGko0Micr7hZp1SfcXxgPhMHl2vdgOsGqDqaWvQsAZLbOPUJ/lbHw5 9LHeU01m/Mw46CvKSODvDG/u7b84mDO/IANxn+dERUD8nxTY0YK8Ag8k1HO9oZ23VM rCeLbVOi5+LY1tE8Hx6MDIACWB/T9Usvsiv0y5Ag= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 297HBEQ7026854 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 7 Oct 2022 12:11:14 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 7 Oct 2022 12:11:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 7 Oct 2022 12:11:14 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 297HBDgi005642; Fri, 7 Oct 2022 12:11:13 -0500 From: Andrew Davis To: Simon Glass , Tom Rini , Vignesh Raghavendra , CC: Andrew Davis Subject: [PATCH 2/3] dma: ti-edma3: Add DMA map operations before and after transfers Date: Fri, 7 Oct 2022 12:11:12 -0500 Message-ID: <20221007171113.31577-2-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221007171113.31577-1-afd@ti.com> References: <20221007171113.31577-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean We should clean the caches before any DMA operation and clean+invalidate after. This matches what the DMA framework does for us already but adds it to the two functions here in this driver that don't yet go through the new DMA framework. Signed-off-by: Andrew Davis --- drivers/dma/ti-edma3.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index ec3dc62d2f..53dc4e8ce5 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -487,8 +488,10 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, { int xfer_len; int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535; + dma_addr_t source; memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer)); + source = dma_map_single(edma_fill_buffer, len, DMA_TO_DEVICE); while (len) { xfer_len = len; @@ -501,6 +504,8 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, len -= xfer_len; dst += xfer_len; } + + dma_unmap_single(source, len, DMA_FROM_DEVICE); } #ifndef CONFIG_DMA @@ -508,13 +513,27 @@ void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len) { + /* Clean the areas, so no writeback into the RAM races with DMA */ + dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE); + dma_addr_t source = dma_map_single(src, len, DMA_TO_DEVICE); + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len); + + /* Clean+Invalidate the areas after, so we can see DMA'd data */ + dma_unmap_single(destination, len, DMA_FROM_DEVICE); + dma_unmap_single(source, len, DMA_TO_DEVICE); } void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, u8 val, size_t len) { + /* Clean the area, so no writeback into the RAM races with DMA */ + dma_addr_t destination = dma_map_single(dst, len, DMA_FROM_DEVICE); + __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len); + + /* Clean+Invalidate the area after, so we can see DMA'd data */ + dma_unmap_single(destination, len, DMA_FROM_DEVICE); } #else -- 2.37.3