From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D9BAC433F5 for ; Fri, 7 Oct 2022 19:22:20 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4E3CA84E89; Fri, 7 Oct 2022 21:22:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="U6z0BTbg"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 647AB84E9D; Fri, 7 Oct 2022 21:22:16 +0200 (CEST) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D4A3984E81 for ; Fri, 7 Oct 2022 21:22:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=afd@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 297JM68u066035; Fri, 7 Oct 2022 14:22:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1665170526; bh=9hxBoMm1sDZOMi6a9fmduubD4lVz1RmUoqsVCur5m5M=; h=From:To:CC:Subject:Date; b=U6z0BTbg7F5ERLxRc7nzk19kkegi6lc/1dB+bIPBJ6F8P4vpHhQ8kELSR2z8rPSMl c9h+qsNmzkYEflYolAWq+FUg6tlV6CJLxVp2IWtk5Sdjc0w1mgqPbO3MkOupPq/r5m 15qTsmtvDNoGkDICO9nbWHA0141vVJNqLBrhG78U= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 297JM6Ml012442 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 7 Oct 2022 14:22:06 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 7 Oct 2022 14:22:06 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 7 Oct 2022 14:22:06 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 297JM53t128565; Fri, 7 Oct 2022 14:22:05 -0500 From: Andrew Davis To: Simon Glass , Tom Rini , Vignesh Raghavendra , Nishanth Menon , CC: Andrew Davis Subject: [PATCH] arm: mach-k3: Move hardware handling to common files Date: Fri, 7 Oct 2022 14:22:05 -0500 Message-ID: <20221007192205.848-1-afd@ti.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean These hardware register definitions are common for all K3, remove duplicate data them by moving them to hardware.h. While here do some minor whitespace cleanup + grouping. Signed-off-by: Andrew Davis --- arch/arm/mach-k3/am642_init.c | 1 - arch/arm/mach-k3/include/mach/am62_hardware.h | 17 ------------ arch/arm/mach-k3/include/mach/am64_hardware.h | 26 ++++--------------- arch/arm/mach-k3/include/mach/am6_hardware.h | 25 +++--------------- arch/arm/mach-k3/include/mach/hardware.h | 19 +++++++++++++- .../arm/mach-k3/include/mach/j721e_hardware.h | 25 +++--------------- .../mach-k3/include/mach/j721s2_hardware.h | 25 +++--------------- 7 files changed, 32 insertions(+), 106 deletions(-) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 8428322ed9..0e30cc47f5 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -23,7 +23,6 @@ #include #include -#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRLMMR_MCU_RST_CTRL 0x04518170 static void ctrl_mmr_unlock(void) diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 9118d05204..278beb587f 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -44,23 +44,6 @@ /* Backup Bootmode USB Config macros */ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism - * shared register definitions. The same registers are also used for - * PADCFG_MMR lock/kick-mechanism. - */ -#define CTRLMMR_LOCK_KICK0 0x1008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK1 0x100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) #define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) #define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index e06e1f9532..6c9332e2bd 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -7,12 +7,13 @@ #ifndef __ASM_ARCH_AM64_HARDWARE_H #define __ASM_ARCH_AM64_HARDWARE_H +#define PADCFG_MMR1_BASE 0x000f0000 +#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x04500000 #define CTRL_MMR0_BASE 0x43000000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) - -#define PADCFG_MMR1_BASE 0xf0000 -#define MCU_PADCFG_MMR1_BASE 0x04080000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 @@ -35,23 +36,6 @@ #define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 -/* - * The CTRL_MMR and PADCFG_MMR memory space is divided into several - * equally-spaced partitions, so defining the partition size allows us to - * determine register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00 /* Use Last 2K as Scratch pad */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index f533e22e06..f9f32918f7 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -13,8 +13,10 @@ #endif #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0) #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) @@ -28,27 +30,6 @@ #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT 9 #define CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK GENMASK(10, 9) -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 028482b3b6..d6d2cf6dc2 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -27,7 +27,7 @@ #endif /* Assuming these addresses and definitions stay common across K3 devices */ -#define CTRLMMR_WKUP_JTAG_ID 0x43000014 +#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 @@ -43,6 +43,23 @@ #define SYS_STATUS_SUB_TYPE_MASK (0xf << 8) #define SYS_STATUS_SUB_TYPE_VAL_FS 0xa +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + #define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT" struct rom_extended_boot_data { diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index b98f0a82f1..032cb2657a 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -12,9 +12,11 @@ #include #endif +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cffb00 diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 23dfe2e9e9..e47f40eac2 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -12,9 +12,11 @@ #include #endif +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 #define CTRL_MMR0_BASE 0x00100000 -#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) #define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) #define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 #define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) @@ -24,33 +26,12 @@ #define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) #define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 -#define WKUP_CTRL_MMR0_BASE 0x43000000 -#define MCU_CTRL_MMR0_BASE 0x40f00000 - #define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) #define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 #define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) #define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 -/* - * The CTRL_MMR0 memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. - */ -#define CTRL_MMR0_PARTITION_SIZE 0x4000 - -/* - * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism - * shared register definitions. - */ -#define CTRLMMR_LOCK_KICK0 0x01008 -#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 -#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) -#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 -#define CTRLMMR_LOCK_KICK1 0x0100c -#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a - /* ROM HANDOFF Structure location */ #define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00 -- 2.37.3