From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC3C8C433FE for ; Tue, 11 Oct 2022 11:52:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3827584F20; Tue, 11 Oct 2022 13:51:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="M9wQ+B4g"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1CC6084D22; Tue, 11 Oct 2022 13:50:54 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 58F5084D22 for ; Tue, 11 Oct 2022 13:50:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 20409610AB; Tue, 11 Oct 2022 11:50:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FBADC433C1; Tue, 11 Oct 2022 11:50:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665489047; bh=CEN5L7FSXkDnvOApFm8lAdDzEbOdBeDBRsYgykTerXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M9wQ+B4ghDNNq0SX+Cor/YYgWnViT+3AEyywIeh0Ty8+p5K7sH1Kss/CWy4ysu/22 84Qpm96tAVDIlupojI7GDZZlEhxG15ZWhegPZA3IzwdypAXb84L1hzyYqmSlNMhW2u WOl/V7RpK0MqA9E5YjfQlTTQaNejbZ6En2QURJsqpuQopa1QJzj97cnZCEYfB7M4it eqKyFxdx5IM2095knjT9EPQE2fU0aLaP2SJoBe1Lna8MWTrgAGtSbK3r1neyM3Gar4 8I8n+Y5AZIsOoHpsdMQWjp0Gsj11wSxFAdMyhj5AUONL5fl7vqhFpd7M/EgZeeuvPw KHLgoqA/Y8d6Q== From: Roger Quadros To: dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, trini@konsulko.com Cc: u-boot@lists.denx.de, Roger Quadros Subject: [u-boot][PATCH 10/14] mtd: rawnand: omap_gpmc: support u-boot driver model Date: Tue, 11 Oct 2022 14:50:08 +0300 Message-Id: <20221011115012.6181-11-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011115012.6181-1-rogerq@kernel.org> References: <20221011115012.6181-1-rogerq@kernel.org> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Adds driver model support. We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT. Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set. Signed-off-by: Roger Quadros --- drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 55 +++++++++++++++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index bc5cabdfc2..1d23144ce4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -190,6 +190,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 + select SYS_NAND_SELF_INIT if ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index e772a914c8..7192ca9e5a 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) * nand_scan about special functionality. See the defines for further * explanation */ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,55 @@ int board_nand_init(struct nand_chip *nand) return 0; } + +static struct nand_chip *nand_chip; /* First NAND chip for SPL use only */ + +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) + +static int gpmc_nand_probe(struct udevice *dev) +{ + struct nand_chip *nand = dev_get_priv(dev); + struct mtd_info *mtd = nand_to_mtd(nand); + int ret; + + gpmc_nand_init(nand); + + ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); + if (ret) + return ret; + + ret = nand_register(0, mtd); + if (ret) + return ret; + + if (!nand_chip) + nand_chip = nand; + + return 0; +} + +static const struct udevice_id gpmc_nand_ids[] = { + { .compatible = "ti,am64-nand" }, + { .compatible = "ti,omap2-nand" }, + { } +}; + +U_BOOT_DRIVER(gpmc_nand) = { + .name = "gpmc-nand", + .id = UCLASS_MTD, + .of_match = gpmc_nand_ids, + .probe = gpmc_nand_probe, + .priv_auto = sizeof(struct nand_chip), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(gpmc_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret); +} +#endif /* CONFIG_SYS_NAND_SELF_INIT */ -- 2.17.1