From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6E6CC433F5 for ; Tue, 11 Oct 2022 11:51:27 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 40B8A84EE8; Tue, 11 Oct 2022 13:51:03 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="fHCmMltF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8774284F06; Tue, 11 Oct 2022 13:50:44 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E9E7684D22 for ; Tue, 11 Oct 2022 13:50:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B8ACD6114E; Tue, 11 Oct 2022 11:50:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC150C433B5; Tue, 11 Oct 2022 11:50:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665489036; bh=qLP09umDGnDY3W0MYiCKYT8buhciMxRf76FO8uaatNE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fHCmMltF3o9I9is9oHb4HlrnU1fz0r8QUgs4bq7FgknWyfIpXO1wvYO2GLPqD1FWh 06dPYKvfQ/ANKU9jfzNMmjoi79Smhi9vHoLbtVPg4+xoPjIS/FfRdFok41rqsQsyL3 oQ6kuChvgNrK+Osdmr3Js9rKkb9dzoHD931WQLLsJxqu+z45LQgz4WWIYcsGqXHrvG XgqZ963MxvqrRr0YUZZwWD7wS+TgHR38jao8/EDYiOv9DQdlQtocY5rin8jaF3Bxe6 bmWurEs9IyLUzs/77/+uv/JWqrQd0Fp/v5mKnoTMTU74c6ZsUSgIdrSCJz3xQqm//D YQ/qKdRIw0kzQ== From: Roger Quadros To: dario.binacchi@amarulasolutions.com, michael@amarulasolutions.com, trini@konsulko.com Cc: u-boot@lists.denx.de, Roger Quadros Subject: [u-boot][PATCH 04/14] mtd: rawnand: omap_gpmc: Optimize NAND reads Date: Tue, 11 Oct 2022 14:50:02 +0300 Message-Id: <20221011115012.6181-5-rogerq@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011115012.6181-1-rogerq@kernel.org> References: <20221011115012.6181-1-rogerq@kernel.org> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Rename omap_nand_read() to omap_nand_read_buf() to reflect actual behaviour. Use FIFO read address instead of raw read address for reads. The GPMC automatically converts 32-bit/16-bit reads to NAND device specific reads (8/16 bit). Use the largest possible read granularity size for more efficient reads. Signed-off-by: Roger Quadros --- drivers/mtd/nand/raw/omap_gpmc.c | 49 ++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index d62c3e6fce..b36fe762b3 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -55,6 +55,7 @@ struct omap_nand_info { enum omap_ecc ecc_scheme; uint8_t cs; uint8_t ws; /* wait status pin (0,1) */ + void __iomem *fifo; }; /* We are wasting a bit of memory but al least we are safe */ @@ -350,6 +351,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; } +static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 alignment = ((uintptr_t)buf | len) & 3; + + if (alignment & 1) + readsb(info->fifo, buf, len); + else if (alignment & 3) + readsw(info->fifo, buf, len >> 1); + else + readsl(info->fifo, buf, len >> 2); +} + #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH #define PREFETCH_CONFIG1_CS_SHIFT 24 @@ -415,7 +430,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt); for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CONFIG_SYS_NAND_BASE); + *buf++ = readl(info->fifo); len -= 4; } } while (len); @@ -425,16 +440,6 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le return 0; } -static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->options & NAND_BUSWIDTH_16) - nand_read_buf16(mtd, buf, len); - else - nand_read_buf(mtd, buf, len); -} - static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) { int ret; @@ -447,7 +452,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) */ head = ((uintptr_t)buf) % 4; if (head) { - omap_nand_read(mtd, buf, head); + omap_nand_read_buf(mtd, buf, head); buf += head; len -= head; } @@ -461,10 +466,10 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); if (ret < 0) { /* fallback in case the prefetch engine is busy */ - omap_nand_read(mtd, buf, len); + omap_nand_read_buf(mtd, buf, len); } else if (tail) { buf += len - tail; - omap_nand_read(mtd, buf, tail); + omap_nand_read_buf(mtd, buf, tail); } } #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ @@ -1001,6 +1006,8 @@ int board_nand_init(struct nand_chip *nand) int32_t gpmc_config = 0; int cs = cs_next++; int err = 0; + struct omap_nand_info *info; + /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -1029,9 +1036,12 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - omap_nand_info[cs].control = NULL; - omap_nand_info[cs].cs = cs; - omap_nand_info[cs].ws = wscfg[cs]; + + info = &omap_nand_info[cs]; + info->control = NULL; + info->cs = cs; + info->ws = wscfg[cs]; + info->fifo = (void __iomem *)CONFIG_SYS_NAND_BASE; nand_set_controller_data(nand, &omap_nand_info[cs]); nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; @@ -1062,10 +1072,7 @@ int board_nand_init(struct nand_chip *nand) #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH nand->read_buf = omap_nand_read_prefetch; #else - if (nand->options & NAND_BUSWIDTH_16) - nand->read_buf = nand_read_buf16; - else - nand->read_buf = nand_read_buf; + nand->read_buf = omap_nand_read_buf; #endif nand->dev_ready = omap_dev_ready; -- 2.17.1