From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D5A2C4332F for ; Fri, 14 Oct 2022 11:11:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 909D184EAF; Fri, 14 Oct 2022 13:11:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5BAA384F2F; Fri, 14 Oct 2022 09:00:35 +0200 (CEST) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D13D384EF9 for ; Fri, 14 Oct 2022 09:00:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peterlin@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 29E70Pdn069783 for ; Fri, 14 Oct 2022 15:00:25 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 14 Oct 2022 15:00:23 +0800 From: Yu Chien Peter Lin To: CC: , , Yu Chien Peter Lin Subject: [PATCH] riscv: andes_plic.c: use modified IPI scheme Date: Fri, 14 Oct 2022 15:00:18 +0800 Message-ID: <20221014070018.30280-1-peterlin@andestech.com> X-Mailer: git-send-email 2.38.0.68.ge85701b4af.dirty MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 29E70Pdn069783 X-Mailman-Approved-At: Fri, 14 Oct 2022 13:11:02 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by: Yu Chien Peter Lin --- arch/riscv/lib/andes_plic.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 5e113ee8c9..9fe2568a16 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -27,17 +27,18 @@ /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) -#define ENABLE_HART_IPI (0x80808080) -#define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) +#define ENABLE_HART_IPI (0x01010101) +#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) DECLARE_GLOBAL_DATA_PTR; -static int enable_ipi(int hart) +int enable_ipi(int hart) { unsigned int en; - en = ENABLE_HART_IPI >> hart; + en = ENABLE_HART_IPI << hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); return 0; } -- 2.34.1