From: Andre Przywara <andre.przywara@arm.com>
To: Jesse Taube <mr.bossman075@gmail.com>
Cc: "Clément Péron" <peron.clem@gmail.com>,
"Jagan Teki" <jagan@amarulasolutions.com>,
"Icenowy Zheng" <uwu@icenowy.me>, "Yifan Gu" <me@yifangu.com>,
"Giulio Benetti" <giulio.benetti@benettiengineering.com>,
"George Hilliard" <thirtythreeforty@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
u-boot@lists.denx.de, linux-sunxi@lists.linux.dev
Subject: Re: [PATCH 6/6] sunxi: add CherryPi-F1C200s support
Date: Tue, 18 Oct 2022 15:01:15 +0100 [thread overview]
Message-ID: <20221018150115.506e449a@donnerap.cambridge.arm.com> (raw)
In-Reply-To: <142d084b-2950-515c-85ea-0f9c82748580@gmail.com>
On Fri, 14 Oct 2022 01:04:18 -0400
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi Jesse, Giulio,
thanks for having a look and for the testing!
> On 10/13/22 05:53, Andre Przywara wrote:
> > On 13/10/2022 09:33, Clément Péron wrote:
> >
> > Hi Clément,
> >
> >> On Wed, 12 Oct 2022 at 18:35, Andre Przywara <andre.przywara@arm.com> wrote:
> >>>
> >>> The CherryPi F1C200s board is a small development board, featuring the
> >>> F1C200s with 64MB of co-packaged DRAM. It comes with two USB-C sockets,
> >>> of which one is connected to a USB-UART chip, that provides easy access
> >>> to UART1.
> >>
> >> A similar board is trying to been upstreamed by Icenowy:
> >>
> >> see : https://lore.kernel.org/lkml/20221012055602.1544944-11-uwu@icenowy.me/
> >> [PATCH v2 10/10] ARM: dts: suniv: add device tree for PopStick v1.1
> >>
> >> Maybe we should take into account the remarks that Krzysztof Kozlowski
> >> made to follow the same device-tree rules on U-boot.
> >
> > Yeah, thanks for the heads up, I saw that. I just wanted to post this to
> > demonstrate what needs to be done. I will be sending a Linux DT patch
> > anyway, since DTs need to go via Linux anyway.
> >
> > Thanks,
> > Andre
> >
> >>
> >> Regards,
> >> Clement
> >>
> >>> Beside the usual micro-SD card slot, the board comes with a SPI NAND
> >>> flash chip, which is not yet supported.
> >>>
> >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >>> ---
> >>> .../dts/suniv-f1c100s-cherrypi-f1c200s.dts | 45 +++++++++++++++++++
> >>> configs/cherrypi_f1c200s_defconfig | 11 +++++
> >>> 2 files changed, 56 insertions(+)
> >>> create mode 100644 arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
> >>> create mode 100644 configs/cherrypi_f1c200s_defconfig
> >>>
> >>> diff --git a/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
> >>> new file mode 100644
> >>> index 00000000000..f0ebcb6d893
> >>> --- /dev/null
> >>> +++ b/arch/arm/dts/suniv-f1c100s-cherrypi-f1c200s.dts
> >>> @@ -0,0 +1,45 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> >>> +/*
> >>> + * Copyright 2022 Arm Ltd.
> >>> + * based on another DT, which is:
> >>> + * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
> Her email changed IDK if it is proper to change here.
> >>> + */
> >>> +
> >>> +/dts-v1/;
> >>> +#include "suniv-f1c100s.dtsi"
> >>> +
> >>> +/ {
> >>> + model = "Cherry Pi F1C200s";
> >>> + compatible = "lctech,cherrypi-f1c200s", "allwinner,suniv-f1c100s";
> >>> +
> >>> + aliases {
> >>> + mmc0 = &mmc0;
> >>> + serial0 = &uart1;
> >>> + spi0 = &spi0;
> no need for spi.
> >>> + };
> >>> +
> >>> + chosen {
> >>> + stdout-path = "serial0:115200n8";
> >>> + };
> >>> +
> >>> + reg_vcc3v3: vcc3v3 {
> >>> + compatible = "regulator-fixed";
> >>> + regulator-name = "vcc3v3";
> >>> + regulator-min-microvolt = <3300000>;
> >>> + regulator-max-microvolt = <3300000>;
> >>> + };
> >>> +};
> >>> +
> >>> +&mmc0 {
> >>> + broken-cd;
> >>> + bus-width = <4>;
> >>> + disable-wp;
> >>> + status = "okay";
> >>> + vmmc-supply = <®_vcc3v3>;
> >>> +};
> >>> +
> >>> +&uart1 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&uart1_pa_pins>;
> >>> + status = "okay";
> >>> +};
> >>> diff --git a/configs/cherrypi_f1c200s_defconfig b/configs/cherrypi_f1c200s_defconfig
> >>> new file mode 100644
> >>> index 00000000000..306d363f485
> >>> --- /dev/null
> >>> +++ b/configs/cherrypi_f1c200s_defconfig
> >>> @@ -0,0 +1,11 @@
> >>> +CONFIG_ARM=y
> >>> +CONFIG_SYS_DCACHE_OFF=y
> >>> +CONFIG_ARCH_SUNXI=y
> >>> +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-cherrypi-f1c200s"
> >>> +CONFIG_SPL=y
> >>> +CONFIG_MACH_SUNIV=y
> >>> +CONFIG_DRAM_CLK=156
> >>> +CONFIG_DRAM_ZQ=0
> You need
> +CONFIG_SPL_STACK=0x8000
I posted "[PATCH 1/2] sunxi: Kconfig: use SoC-wide values for some symbols"
(https://lore.kernel.org/u-boot/20220913234335.24902-2-andre.przywara@arm.com/)
that solves that issue.
That patch is applied before this series in the tree, so no change should
be needed.
Thanks for the report!
Cheers,
Andre
>
> I will test this on both 100s and 200s.
> Thanks,
> Jesse Taube
> >>> +CONFIG_SUNXI_MINIMUM_DRAM_MB=64
> >>> +# CONFIG_VIDEO_SUNXI is not set
> >>> +CONFIG_CONS_INDEX=2
> >>> --
> >>> 2.25.1
> >>>
> >>>
> >
next prev parent reply other threads:[~2022-10-18 14:01 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-12 16:34 [PATCH 0/6] sunxi: improve F1C200s support Andre Przywara
2022-10-12 16:34 ` [PATCH 1/6] sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MB Andre Przywara
2022-10-12 21:33 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 2/6] sunxi: fix 32MB load address layout Andre Przywara
2022-10-12 21:37 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 3/6] sunxi: f1c100: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig Andre Przywara
2022-10-12 21:38 ` Jernej Škrabec
2022-10-13 8:51 ` Icenowy Zheng
2022-10-12 16:34 ` [PATCH 4/6] sunxi: f1c100: add UART1 support Andre Przywara
2022-10-12 21:42 ` Jernej Škrabec
2022-10-18 9:23 ` Andre Przywara
2022-10-19 3:55 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 5/6] sunxi: f1c100: dtsi: add UART1 pins Andre Przywara
2022-10-12 21:43 ` Jernej Škrabec
2022-10-12 16:34 ` [PATCH 6/6] sunxi: add CherryPi-F1C200s support Andre Przywara
2022-10-13 8:33 ` Clément Péron
2022-10-13 9:53 ` Andre Przywara
2022-10-14 5:04 ` Jesse Taube
2022-10-18 14:01 ` Andre Przywara [this message]
2022-10-20 15:52 ` Giulio Benetti
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