From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0BABC38A2D for ; Tue, 25 Oct 2022 07:52:03 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5A71D84D25; Tue, 25 Oct 2022 09:51:46 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="h0ibl1xi"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 58B2084D21; Tue, 25 Oct 2022 09:51:33 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D735E806C8 for ; Tue, 25 Oct 2022 09:51:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Conor.Dooley@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666684276; x=1698220276; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=AEXvOgBU7ZxSOCoacqSvOiKhdhbOosipF+EU826JKSE=; b=h0ibl1xiBldjsPCUnngVngozjsw5qXxJvqZUvhSh++HIyGzPihgXb+yI SiCAPT2VW91EX5kUKc7KPpE26eur4Q6xCzqE9GmIP6mXU3x4nPQG9LdnJ uAhXUH0iAnCeSs+ik7q5+tEwGZ9dihM4YccjZRHJbwe+YtZr6BTlG9f1d V6qcSyed4z2e7A+GwEw4coxhywKy4QVgg52c1k2EmDFD5PmkfxH8kYaaY kbBV3Ufo6JWVTtTP9421mIrVJBCeDochsJWUAsnvh9/z1mLGEEXuHOvFm oQlHLWCXRSYL1NO5FedHmZ8dCqQFQSS52cUI5IZQDZzf/zcYl94st4g/N g==; X-IronPort-AV: E=Sophos;i="5.95,211,1661842800"; d="scan'208";a="186266370" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Oct 2022 00:51:12 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 25 Oct 2022 00:51:12 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 25 Oct 2022 00:51:11 -0700 From: Conor Dooley To: Rick Chen , Leo , "Lukasz Majewski" , Sean Anderson CC: Conor Dooley , Padmarao Begari , Subject: [PATCH v1 0/6] clk: microchip: mpfs: incremental fixes Date: Tue, 25 Oct 2022 08:58:43 +0100 Message-ID: <20221025075848.110754-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hey All, When trying to sync the Linux device tree with U-Boot, the clock driver's expectation that the input clock it gets is the mss pll presented itself as a problem. The mss pll is not a fixed frequency clock and the Linux devicetree has the actual off-chip oscillator & the clock driver there uses that. This had gone un-noticed in the original dt upstreaming to Linux and I noticed it while upstreaming the clock driver there. I order to switch the clock driver over to using the real reference, we first need to switch over from reading a property of what we assume to be a fixed-frequency clock in the device tree to using clk_get_rate() and fix the parentage of the "periph" clocks to represent their actual relationships to their parents rather than using this fixed-frequency clock in the devicetree to determine their rates. With that done, we can then introduce a small driver for the msspll itself, which we will use if the corrected devicetree node for the clock controller is present. There are some more fixes required, specifically handling of the mtimer clock and of the refclk for the rtc which I have not addressed here, but will deal with in a follow-up series. I've omitted these fixes here to do just what is needed to unblock the dt sync. Thanks, Conor. Conor Dooley (6): dt-bindings: clk: add missing clk ids for microchip mpfs clk: microchip: mpfs: convert parent rate acquistion to get_get_rate() clk: microchip: mpfs: fix reference clock handling clk: microchip: mpfs: fix periph clk parentage clk: microchip: mpfs: fix criticality of peripheral clocks riscv: dts: fix the mpfs's reference clock frequency arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 + arch/riscv/dts/microchip-mpfs.dtsi | 14 +-- drivers/clk/microchip/Makefile | 2 +- drivers/clk/microchip/mpfs_clk.c | 37 ++++-- drivers/clk/microchip/mpfs_clk.h | 20 +-- drivers/clk/microchip/mpfs_clk_cfg.c | 7 +- drivers/clk/microchip/mpfs_clk_msspll.c | 119 ++++++++++++++++++ drivers/clk/microchip/mpfs_clk_periph.c | 96 +++++++------- .../dt-bindings/clock/microchip-mpfs-clock.h | 3 + 9 files changed, 229 insertions(+), 73 deletions(-) create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c -- 2.38.0