From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04BABC4332F for ; Sat, 5 Nov 2022 04:25:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 18DC085200; Sat, 5 Nov 2022 05:24:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lzUfzRl2"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1399F851E2; Sat, 5 Nov 2022 05:24:41 +0100 (CET) Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 5F69585200 for ; Sat, 5 Nov 2022 05:24:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=judge.packham@gmail.com Received: by mail-pj1-x1035.google.com with SMTP id l22-20020a17090a3f1600b00212fbbcfb78so9913767pjc.3 for ; Fri, 04 Nov 2022 21:24:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+gAegBUpQ+3sI9KK0cZFWpAVjkowQGDWsdraMSJXkPc=; b=lzUfzRl2iSeJKUIX9jmNf8s/K55Wx0kmg9oSIYkzqVwabCKwzYTRLoWZre1BvThneR 3ZzBsuPyBhRo+vJ6B6KG1dQvZQzKbQIbSppGKF96GrxHz4IYtL+U3hYLqB9LitysuLHJ O+fGePZzJiTwIbFwOYtvmlfaW3WzoTBu8t6scWdvwpL8t+q3/3QUqG1d/N+BVPpYPASs 4pujNBt3nmeE1V8zrCQ6NXez1rA4bSKXuOg6rflkOge+RD3ql4ZoNLfiI1WNbz/Rzu87 AmyyvJBBYwoS+Sg0sWybwnl8W2kpvFO5aizAqX+pn5R+Kzejhdp6gFPavsFxcUouBjyE Km8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+gAegBUpQ+3sI9KK0cZFWpAVjkowQGDWsdraMSJXkPc=; b=4DEPjrpHfYlmTQSQ0CqDjbDmABV69HVC/We36Dl8HnpM/aU0BJYobQf4DpJjDfWxo5 5H6uUUFSXwHAhTReKm37Oc/35BsQBl1B8k6djuaelmonsCkUMghGvBdHYMWExz8rwX6l NGFpyxrt5a6YEi1NBYDbfkNVuV1E2FdnNFXZ0rSFC+yj/CVvWQ36bB98QU/Vi6jPfVzn moREx9Y0jTJH0Q6c/t+22QBe+aqROsKAlV0If+PVerNPG71goWDZ9LNXH3I51AeeLd0F XIDxUSRaqk86YrwwEc7x3eNeKK8Op3BIH1wPu9Ws5W4DgLY1zq14wfDN7wECfor/u6H8 AcBA== X-Gm-Message-State: ACrzQf13+uT2OuybWnhItsjx4bb4xF8WacaFgxjOHPMWChI8UktYo2HM 7VU/AbfIpnEuiPMCwcp/hqo= X-Google-Smtp-Source: AMsMyM59vbOINBzjZp+j5hwUbSWp5DZsASz1rAvclN9FwLG5uYzFaBNmMjndYwwaLCM5UQbcrIYWLA== X-Received: by 2002:a17:902:7283:b0:188:612b:1d31 with SMTP id d3-20020a170902728300b00188612b1d31mr8117208pll.81.1667622270563; Fri, 04 Nov 2022 21:24:30 -0700 (PDT) Received: from chrisp-dl.atlnz.lc ([2001:df5:b000:22:89de:4dc7:b348:99d]) by smtp.gmail.com with ESMTPSA id p67-20020a625b46000000b005625d6d2999sm384126pfb.187.2022.11.04.21.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 21:24:29 -0700 (PDT) From: Chris Packham To: Stefan Roese Cc: Elad Nachman , Vadym Kochan , Chris Packham , Adam Ford , Jim Liu , Lukasz Majewski , Marek Vasut , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Weijie Gao , u-boot@lists.denx.de Subject: [PATCH v6 3/6] usb: ehci: ehci-marvell: Support for marvell,ac5-ehci Date: Sat, 5 Nov 2022 17:23:57 +1300 Message-Id: <20221105042400.277650-4-judge.packham@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221105042400.277650-1-judge.packham@gmail.com> References: <20221105042400.277650-1-judge.packham@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with the fact that the ac5 does not have the mbus infrastructure the 32-bit SoCs have and ensure USB_EHCI_IS_TDI is selected. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- (no changes since v5) Changes in v5: - Minor white space cleanups - Collect review from Stefan drivers/usb/host/Kconfig | 1 + drivers/usb/host/ehci-marvell.c | 53 ++++++++++++++++++++++++++++----- 2 files changed, 46 insertions(+), 8 deletions(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 1aabe062fb..c750b0207d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -178,6 +178,7 @@ config USB_EHCI_MARVELL depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X default y select USB_EHCI_IS_TDI if !ARM64 + select USB_EHCI_IS_TDI if ALLEYCAT_5 ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index b7e60c690a..6093c8fb0b 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -48,12 +48,17 @@ struct ehci_mvebu_priv { fdt_addr_t hcd_base; }; +#define USB_TO_DRAM_TARGET_ID 0x2 +#define USB_TO_DRAM_ATTR_ID 0x0 +#define USB_DRAM_BASE 0x00000000 +#define USB_DRAM_SIZE 0xfff /* don't overrun u-boot source (was 0xffff) */ + /* * Once all the older Marvell SoC's (Orion, Kirkwood) are converted * to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup(void *base) +static void usb_brg_adrdec_setup(struct udevice *dev, void *base) { const struct mbus_dram_target_info *dram; int i; @@ -65,16 +70,34 @@ static void usb_brg_adrdec_setup(void *base) writel(0, base + USB_WINDOW_BASE(i)); } - for (i = 0; i < dram->num_cs; i++) { - const struct mbus_dram_window *cs = dram->cs + i; + if (device_is_compatible(dev, "marvell,ac5-ehci")) { + /* + * use decoding window to map dram address seen by usb to 0x0 + */ /* Write size, attributes and target id to control register */ - writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | - (dram->mbus_dram_target_id << 4) | 1, - base + USB_WINDOW_CTRL(i)); + writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) | + (USB_TO_DRAM_TARGET_ID << 4) | 1, + base + USB_WINDOW_CTRL(0)); /* Write base address to base register */ - writel(cs->base, base + USB_WINDOW_BASE(i)); + writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0)); + + debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n", + base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)), + base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0))); + } else { + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + USB_WINDOW_CTRL(i)); + + /* Write base address to base register */ + writel(cs->base, base + USB_WINDOW_BASE(i)); + } } } @@ -126,7 +149,7 @@ static int ehci_mvebu_probe(struct udevice *dev) if (device_is_compatible(dev, "marvell,armada-3700-ehci")) marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup; else - usb_brg_adrdec_setup((void *)priv->hcd_base); + usb_brg_adrdec_setup(dev, (void *)priv->hcd_base); hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); hcor = (struct ehci_hcor *) @@ -136,6 +159,19 @@ static int ehci_mvebu_probe(struct udevice *dev) (uintptr_t)hccr, (uintptr_t)hcor, (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); +#define PHY_CALIB_OFFSET 0x808 + /* + * Trigger calibration during each usb start/reset: + * BIT 13 to 0, and then to 1 + */ + if (device_is_compatible(dev, "marvell,ac5-ehci")) { + void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET); + u32 val = readl(phy_calib_reg) & (~BIT(13)); + + writel(val, phy_calib_reg); + writel(val | BIT(13), phy_calib_reg); + } + return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0, USB_INIT_HOST); } @@ -143,6 +179,7 @@ static int ehci_mvebu_probe(struct udevice *dev) static const struct udevice_id ehci_usb_ids[] = { { .compatible = "marvell,orion-ehci", }, { .compatible = "marvell,armada-3700-ehci", }, + { .compatible = "marvell,ac5-ehci", }, { } }; -- 2.38.1