From: Dylan Hung <dylan_hung@aspeedtech.com>
To: <ryan_chen@aspeedtech.com>, <chiawei_wang@aspeedtech.com>,
<joel@jms.id.au>, <dylan_hung@aspeedtech.com>,
<u-boot@lists.denx.de>
Cc: <BMC-SW@aspeedtech.com>
Subject: [PATCH 1/3] ram: ast2600: Fix incorrect statement of the register polling
Date: Fri, 11 Nov 2022 15:30:06 +0800 [thread overview]
Message-ID: <20221111073008.16364-2-dylan_hung@aspeedtech.com> (raw)
In-Reply-To: <20221111073008.16364-1-dylan_hung@aspeedtech.com>
The condition "~data" in the if-statement is a typo. The original
intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use
"data == 0" for instead.
Besides, the bit[1] of "phy_status" register is hardwired to
SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has
already done, remove the unnecessary checking of phy_status[1].
Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support")
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
---
drivers/ram/aspeed/sdram_ast2600.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 9ad398d24155..b09232a30413 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -449,7 +449,7 @@ static void ast2600_sdramphy_kick_training(struct dram_info *info)
while (1) {
data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
- if (~data)
+ if (data == 0)
break;
}
}
@@ -984,11 +984,6 @@ static int ast2600_sdrammc_probe(struct udevice *dev)
L_ast2600_sdramphy_train:
ast2600_sdrammc_init_ddr4(priv);
- /* make sure DDR-PHY is ready before access */
- do {
- reg = readl(priv->phy_status) & BIT(1);
- } while (reg == 0);
-
if (ast2600_sdramphy_check_status(priv) != 0) {
printf("DDR4 PHY training fail, retrain\n");
goto L_ast2600_sdramphy_train;
--
2.25.1
next prev parent reply other threads:[~2022-11-11 7:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 7:30 [PATCH 0/3] Improve AST26x0 DDR4 timing and signal quality Dylan Hung
2022-11-11 7:30 ` Dylan Hung [this message]
2022-11-24 1:22 ` [PATCH 1/3] ram: ast2600: Fix incorrect statement of the register polling Ryan Chen
2022-11-24 21:33 ` Tom Rini
2022-11-11 7:30 ` [PATCH 2/3] ram: ast2600: Improve ddr4 timing and signal quality Dylan Hung
2022-11-24 1:22 ` Ryan Chen
2022-11-24 21:33 ` Tom Rini
2022-11-11 7:30 ` [PATCH 3/3] ram: ast2600: Align the RL and WL setting Dylan Hung
2022-11-24 1:23 ` Ryan Chen
2022-11-24 21:33 ` Tom Rini
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