From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D742DC4332F for ; Sun, 13 Nov 2022 13:56:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3A46C85174; Sun, 13 Nov 2022 14:56:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="emHCI1bE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9AA6B8517B; Sun, 13 Nov 2022 14:55:57 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7FDB385170 for ; Sun, 13 Nov 2022 14:55:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668347750; x=1699883750; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5YnHdZXCLgraHKtHyfFJFdGlOPGWRj3zWyYniakJUz0=; b=emHCI1bEQbgyCSmCGfo1DICqZ9lgk4evDio8yp8cznUArm6HeD/yfDBZ T8tdiOTzWtr7RlHzof8now8yR04TUSy6Er1xWxaHc1HKqIyXpGqDRGlkY hf6ukpnhy/bVaXvVz+k07QbfvJ1sZMHOD5M6r+ea2q4wx3v6EAMkhamUp LT5FcsIbNBG37CmVuDgEAM+UUtfEFzGV3whme+O1++tK3Tf+1Up2NTG7o WiXN37utmv89uUxl8u8nm5QO/YOTc9LWfge10Yve+lTCXu8woph33UXrr ZfIHjKfqTuK9sHf4nBpU4DXmous95x+ES41Ct7SG9lJSAap/N+h1ZiCt0 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="292211352" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="292211352" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 05:55:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="763166447" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="763166447" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga004.jf.intel.com with ESMTP; 13 Nov 2022 05:55:43 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 8B4123559; Sun, 13 Nov 2022 21:55:42 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 8A95AE0094D; Sun, 13 Nov 2022 21:55:42 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Lokanathan@ecsmtp.png.intel.com Subject: [PATCH 3/4] doc: README.socfpga: Update for U-boot 2022.04 Date: Sun, 13 Nov 2022 21:55:35 +0800 Message-Id: <20221113135536.9920-3-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221113135536.9920-1-jit.loon.lim@intel.com> References: <20221113135536.9920-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: "Lokanathan, Raaj" Update the tested Intel Quartus Software versions and highlight the major changes in this U-boot version. Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- doc/README.socfpga | 104 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 82 insertions(+), 22 deletions(-) diff --git a/doc/README.socfpga b/doc/README.socfpga index a469cc7e41..362361e014 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -15,6 +15,8 @@ Table of Contents 4. Cyclone V / Arria V generating the handoff header files for U-Boot SPL 5. Arria10 generating the handoff header files for U-Boot SPL 6. mkimage for Cyclone V, Arria V and Arria 10 + 7. SDRAM secure region in U-boot ATF flow + 8. binman for U-boot ATF flow 1. Device Family Support vs Tested Intel Quartus @@ -22,19 +24,18 @@ Table of Contents Processor SOCFPGA Device Family Intel Quartus Prime Pro Edition Intel Quartus Prime Standard Edition -------------------------------------------------------------------------------------------------------------------------------------------- - Dual-core ARM Cortex-A9 Cyclone V N/A 20.1 - Arria V N/A 20.1 - Arria 10 20.1, 20.3 20.1 + Dual-core ARM Cortex-A9 Cyclone V N/A 21.1 + Arria 10 22.1 N/A - Quad-core ARM Cortex-A53 Stratix 10 20.1, 20.2, 20.3 N/A - Agilex 20.1, 20.2, 20.3 N/A - Diamond Mesa Early access N/A + Quad-core ARM Cortex-A53 Stratix 10 22.1 N/A + Agilex 22.1 N/A + eASIC N5X 22.1 N/A 2. Feature Support --------------------------------------------------------------------- - Hardware Feature Cyclone V Arria 10 Stratix 10 Agilex Diamond Mesa + Hardware Feature Cyclone V Arria 10 Stratix 10 Agilex eASIC N5X Arria V -------------------------------------------------------------------------------------------------------------------- SDRAM Yes Yes Yes Yes Yes @@ -53,29 +54,23 @@ Table of Contents Denali NAND controller No Yes Yes Yes Yes --------------------------------------------------------------------------------------------------------------------- - Software Feature Cyclone V Arria 10 Stratix 10 Agilex Diamond Mesa + Software Feature Cyclone V Arria 10 Stratix 10 Agilex eASIC N5X Arria V --------------------------------------------------------------------------------------------------------------------- - Remote System Update (RSU) No No Yes Yes No - ARM Trusted Firmware (ATF) No No Yes Yes Yes + Remote System Update (RSU) [1] No No Yes Yes No + ARM Trusted Firmware (ATF) [2] No No Yes Yes Yes Vendor Authorized Boot (VAB) No No No No Yes --------------------------------------------------------------------------------------------------------------------- + Notes: + [1] RSU SPT/CPB recovery features are supported with Quartus version 20.4 onwards + [2] ATF boot flow is supported with altera-opensource/arm-trusted-firmware branch:socfpga_v2.3 onwards + 3. Major Changes and Known Issues --------------------------------------------------------------------- - 3.1 Support 'vab' command to perform vendor authentication. - - Command format: vab addr len - Authorize 'len' bytes starting at 'addr' via vendor public key - - 3.2 Support SDRAM secure region in U-boot-ATF flow - - First 1 MiB of SDRAM is configured as secure region, other - address spaces are non-secure regions. Only software executing - at secure state EL3 (eg: U-boot SPL) and secure masters are - allowed access to secure region. + 3.1 Upgraded U-boot to version v2022.04 4. Cyclone V / Arria V generating the handoff header files for U-Boot SPL @@ -244,4 +239,69 @@ Table of Contents Arria 10: ./tools/mkimage -T socfpgaimage_v1 -d spl/u-boot-spl.bin spl/u-boot-spl.sfp - For more inforation, run "./tools/mkimage --help". \ No newline at end of file + For more inforation, run "./tools/mkimage --help". + +7. SDRAM secure region in U-boot ATF flow +---------------------------------------------------------- + + In boot flow that uses ATF (ARM trusted firmware), the first 1 MiB of SDRAM + is configured as secure region, other address spaces are non-secure regions. + Only software executing at secure state EL3 (eg: U-boot SPL, ATF) and secure + masters are allowed access to the secure region. + +8. binman for U-boot ATF flow +---------------------------------------------------------- + + Overview + ~~~~~~~~ + + Before v2021.04, we provide *.sh/*.its for user to generate FIT image using + 'mkimage' tool. To align with U-Boot community strategy to eliminate the custom + *.sh/*its script, we have removed all *.sh/*.its files and switched to use + 'binman' tool to generate FIT image for all SOC64 devices (Stratix 10, Agilex, + eASIC N5X) started in U-boot version v2021.04. + + FIT image content is defined in binman node in U-boot device tree (u-boot.dtb). + U-Boot v2021.04 support u-boot.itb and kernel.itb. + + With "CONFIG_BINMAN" enabled in deconfig, U-boot will always run 'binman' tool + before end of the code compilation. If the required input files exists in U-boot + folder, *.itb files defined in u-boot.dtb will be generated. Otherwise, 'binman' + will not generate the *.itb files. You can run 'binman' tool manually via command + line to generate the *.itb file. + + Input Files + ~~~~~~~~~~~ + + Input files for *_atf_defconfig FIT image generation: + To generate u-boot.itb: + u-boot-nodtb.bin + u-boot.dtb + bl31.bin + To generate kernel.itb: + Image + linux.dtb + + Input files for *_vab_defconfig FIT image generation: + To generate u-boot.itb: + signed-u-boot-nodtb.bin + signed-u-boot.dtb + signed-bl31.bin + + To generate kernel.itb: + signed-Image + signed-linux.dtb + + Command Line + ~~~~~~~~~~~~ + + Please use the following commands to generate the u-boot.itb and kernel.itb: + + $ /tools/binman/binman build -u -d u-boot.dtb -O . + This command generate all FIT images that defined in device tree. + + $ /tools/binman/binman build -u -d u-boot.dtb -O . -i u-boot + This command generate u-boot.itb only. + + $ /tools/binman/binman build -u -d u-boot.dtb -O . -i kernel + This command generate kernel.itb only. \ No newline at end of file -- 2.26.2