From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CC49C4332F for ; Sun, 13 Nov 2022 13:56:22 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B7C058516A; Sun, 13 Nov 2022 14:56:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bKVg3HtB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 08DE585170; Sun, 13 Nov 2022 14:55:58 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8EDED85174 for ; Sun, 13 Nov 2022 14:55:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668347750; x=1699883750; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2DAPlL0uzZLL+k/A1Wfo4pOrrsYf+VotWiCusbt4V7s=; b=bKVg3HtBpUt1pcJBzOErhuS0USh+Lq70R7SkpMcCYclFeGwOy6XG0Yz+ YXEDMAm/aHfnlu6uvo/aheqMcNTPEYxENx4yGmp6HdQdi1Q8kJzVaXior VjHj2brR9sfh/x/cRw4a0mqMxcOkx3ugBX5rdcpy9hM/D0o97xMWOZfQH pjvHvabMmydBEZqi2qTyMuYMZSqdW9gSPw3xhEN2cIjxq2YaBdQyYrfUa yZtlayJcR20sofsJ+U0W8uoDSgtxFsFPFV4EOQ6RvY+vUmqDP55/8Ao+s G6Ge0VUnOHogxNYTEThLMlJEOzs3f1E0V3KNhqc+nr6giGRRS4/1nmX8j Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="292211354" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="292211354" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 05:55:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="763166451" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="763166451" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga004.jf.intel.com with ESMTP; 13 Nov 2022 05:55:44 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id ABDEA355A; Sun, 13 Nov 2022 21:55:43 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id A937DE0094D; Sun, 13 Nov 2022 21:55:43 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Yau Wai Gan Subject: [PATCH 4/4] doc: README.socfpga: Add official boot flow support info Date: Sun, 13 Nov 2022 21:55:36 +0800 Message-Id: <20221113135536.9920-4-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221113135536.9920-1-jit.loon.lim@intel.com> References: <20221113135536.9920-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Yau Wai Gan The official boot-up flow for SoC FPGA 64-bit is with Arm Trusted Firmware, ATF BL31. The non-ATF flow is legacy and is not supported officially moving forward. Update the README to include the information. Signed-off-by: Yau Wai Gan Signed-off-by: Jit Loon Lim --- doc/README.socfpga | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/doc/README.socfpga b/doc/README.socfpga index 362361e014..3f0ce8ce7b 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -17,6 +17,7 @@ Table of Contents 6. mkimage for Cyclone V, Arria V and Arria 10 7. SDRAM secure region in U-boot ATF flow 8. binman for U-boot ATF flow + 9. Official Boot-up Flow Support 1. Device Family Support vs Tested Intel Quartus @@ -304,4 +305,31 @@ Table of Contents This command generate u-boot.itb only. $ /tools/binman/binman build -u -d u-boot.dtb -O . -i kernel - This command generate kernel.itb only. \ No newline at end of file + This command generate kernel.itb only. + +9. Official Boot-up Flow Support +--------------------------------------------------------------------- + U-boot with Arm Trusted Firmware (ATF, TF-A) boot-up is the official supported + boot flow for Intel SoC FPGA Arm 64-bit architecture devices including + Stratix 10, Agilex and N5X. ATF is the secure runtime firmware running at EL3 + which handles secure accesses from U-boot proper and Linux running at EL2 and EL1. + + Official boot flow: + U-boot -> ATF BL31 -> U-boot proper -> Linux + + Legacy (aka non ATF) boot flow: + U-boot -> U-boot proper -> Linux + + U-boot version socfpga_v2021.07 and onwards change the defconfig name to match + the official boot flow. The non ATF flow defconfigs are renamed with _legacy_ + appended and is not officially supported moving forward. See details as follow. + + Legacy boot flow: + socfpga_agilex_defconfig -> socfpga_agilex_legacy_defconfig + socfpga_n5x_defconfig -> socfpga_n5x_legacy_defconfig + socfpga_stratix10_defconfig -> socfpga_stratix10_legacy_defconfig + + Official boot flow: + socfpga_agilex_atf_defconfig -> socfpga_agilex_defconfig + socfpga_n5x_atf_defconfig -> socfpga_n5x_defconfig + socfpga_stratix10_atf_defconfig -> socfpga_stratix10_defconfig \ No newline at end of file -- 2.26.2