From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49EA3C433FE for ; Sun, 13 Nov 2022 14:57:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4052E8516A; Sun, 13 Nov 2022 15:57:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Waqm9Qx3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6674C85183; Sun, 13 Nov 2022 15:57:18 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1AB6284C17 for ; Sun, 13 Nov 2022 15:57:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668351435; x=1699887435; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Dv8MLpjZ06yyDUWSPPDPuprNAgqJT87S7Wrxy6QI8aM=; b=Waqm9Qx3zWRvSxI95ucbxgvAeMIjEiLTy572exaqIo+9dpO3WjUSAfpD zTm+JrD0iYnXAwRHa/+g95LsbJPN5f/nlBx2hb/cRPxDn1nNQFj5c71Kb XMNTT0Y1jKAulWgImFvUGyIYLQ71rVKUa1CXQb4Kh6Aam/hwJqmZNvNMM mcpeYOkHKZMvxKjm+UIm9AcLpVUvmJ5xXwMdDkmZO24FW4t4BV8c2TUaH qfbsBeYTqW7SLCZkca551TG3K2Pfx0fMe8u8hLk8yo0D11I3w9AMR7gIB KkuZG9eIGhOOKTKomImqi801h9IU6Hweqe2t0DFfFC98exG6yXWj2teZt A==; X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="292215253" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="292215253" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2022 06:57:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10529"; a="967287416" X-IronPort-AV: E=Sophos;i="5.96,161,1665471600"; d="scan'208";a="967287416" Received: from pglmail07.png.intel.com ([10.221.193.207]) by fmsmga005.fm.intel.com with ESMTP; 13 Nov 2022 06:57:08 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 58E7F4837; Sun, 13 Nov 2022 22:57:08 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 21435E0094D; Sun, 13 Nov 2022 22:57:08 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 1/5] arm: socfpga: Add F2SDRAM_MANAGER base address Date: Sun, 13 Nov 2022 22:57:02 +0800 Message-Id: <20221113145706.5002-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #1508586908-1: Add F2SDRAM Manager base address. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- .../include/mach/reset_manager_soc64.h | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2..ca5739c30c 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2019 Intel Corporation + * Copyright (C) 2016-2022 Intel Corporation */ #ifndef _RESET_MANAGER_SOC64_H_ @@ -12,15 +12,33 @@ void print_reset_info(void); void socfpga_bridges_reset(int enable); #define RSTMGR_SOC64_STATUS 0x00 +#define RSTMGR_SOC64_HDSKEN 0x10 +#define RSTMGR_SOC64_HDSKREQ 0x14 +#define RSTMGR_SOC64_HDSKACK 0x18 #define RSTMGR_SOC64_MPUMODRST 0x20 #define RSTMGR_SOC64_PER0MODRST 0x24 #define RSTMGR_SOC64_PER1MODRST 0x28 #define RSTMGR_SOC64_BRGMODRST 0x2c -#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 +#define RSTMGR_BRGMODRST_SOC2FPGA_MASK BIT(0) +#define RSTMGR_BRGMODRST_LWSOC2FPGA_MASK BIT(1) +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK BIT(2) +#define RSTMGR_BRGMODRST_F2SDRAM0_MASK BIT(3) +#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) +#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) +#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) + +#define BRGMODRST_SOC2FPGA_BRIDGES (RSTMGR_BRGMODRST_SOC2FPGA_MASK | \ + RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) +#define BRGMODRST_FPGA2SOC_BRIDGES (RSTMGR_BRGMODRST_FPGA2SOC_MASK | \ + RSTMGR_BRGMODRST_F2SDRAM0_MASK | \ + RSTMGR_BRGMODRST_F2SDRAM1_MASK | \ + RSTMGR_BRGMODRST_F2SDRAM2_MASK) + +#define RSTMGR_HDSKEN_FPGAHSEN BIT(2) +#define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) /* SDM, Watchdogs and MPU warm reset mask */ #define RSTMGR_STAT_SDMWARMRST BIT(1) -- 2.26.2