* [PATCH 2/5] arm: socfpga: soc64: Update reset manager registers
2022-11-13 14:57 [PATCH 1/5] arm: socfpga: Add F2SDRAM_MANAGER base address Jit Loon Lim
@ 2022-11-13 14:57 ` Jit Loon Lim
2022-11-13 14:57 ` [PATCH 3/5] arm: socfpga: soc64: Move bridges reset to common function Jit Loon Lim
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Jit Loon Lim @ 2022-11-13 14:57 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang, Ley Foon Tan
From: Ley Foon Tan <ley.foon.tan@intel.com>
HSD #1508586908-2: Add reset manager registers, preparation for f2s bridge reset support.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index ca5739c30c..9589b61749 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -29,7 +29,6 @@ void socfpga_bridges_reset(int enable);
#define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4)
#define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5)
#define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6)
-
#define BRGMODRST_SOC2FPGA_BRIDGES (RSTMGR_BRGMODRST_SOC2FPGA_MASK | \
RSTMGR_BRGMODRST_LWSOC2FPGA_MASK)
#define BRGMODRST_FPGA2SOC_BRIDGES (RSTMGR_BRGMODRST_FPGA2SOC_MASK | \
--
2.26.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 3/5] arm: socfpga: soc64: Move bridges reset to common function
2022-11-13 14:57 [PATCH 1/5] arm: socfpga: Add F2SDRAM_MANAGER base address Jit Loon Lim
2022-11-13 14:57 ` [PATCH 2/5] arm: socfpga: soc64: Update reset manager registers Jit Loon Lim
@ 2022-11-13 14:57 ` Jit Loon Lim
2022-11-13 14:57 ` [PATCH 4/5] arm: socfpga: soc64: Add f2s bridge support Jit Loon Lim
2022-11-13 14:57 ` [PATCH 5/5] arm: socfpga: soc64: Avoid hang in bridge reset Jit Loon Lim
3 siblings, 0 replies; 5+ messages in thread
From: Jit Loon Lim @ 2022-11-13 14:57 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang, Ley Foon Tan
From: Ley Foon Tan <ley.foon.tan@intel.com>
HSD #1508586908-3: Move bridges reset code to common function, socfpga_s2f_bridges_reset().
This function is an inline function and can be included in normal U-boot
and psci secure section.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/reset_manager_s10.c | 71 +++++++++++------------
1 file changed, 35 insertions(+), 36 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index f47fec10a0..20ab374881 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -57,32 +57,20 @@ void socfpga_per_reset_all(void)
writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
}
-void socfpga_bridges_reset(int enable)
+static __always_inline void socfpga_s2f_bridges_reset(int enable)
{
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
- u64 arg = enable;
-
- int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
- if (ret) {
- printf("SMC call failed with error %d in %s.\n", ret, __func__);
- return;
- }
-#else
- u32 reg;
-
if (enable) {
/* clear idle request to all bridges */
setbits_le32(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
- /* Release all bridges from reset state */
+ /* Release SOC2FPGA bridges from reset state */
clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
- ~0);
+ BRGMODRST_SOC2FPGA_BRIDGES);
/* Poll until all idleack to 0 */
- read_poll_timeout(readl, reg, !reg, 1000, 300000,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK);
+ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK), 300);
} else {
/* set idle request to all bridges */
writel(~0,
@@ -93,30 +81,41 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- read_poll_timeout(readl, reg,
- reg == (SYSMGR_NOC_H2F_MSK |
- SYSMGR_NOC_LWH2F_MSK),
- 1000, 300000,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLEACK);
-
- /* Poll until all idlestatus to 1 */
- read_poll_timeout(readl, reg,
- reg == (SYSMGR_NOC_H2F_MSK |
- SYSMGR_NOC_LWH2F_MSK),
- 1000, 300000,
- socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_NOC_IDLESTATUS);
-
- /* Reset all bridges (except NOR DDR scheduler & F2S) */
+ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLEACK) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK),
+ 300);
+
+ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_NOC_IDLESTATUS) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK),
+ 300);
+
+ /* Reset all SOC2FPGA bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
- ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
- RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+ BRGMODRST_SOC2FPGA_BRIDGES);
/* Disable NOC timeout */
writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
}
-#endif
+}
+
+void socfpga_bridges_reset(int enable)
+{
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ u64 arg = enable;
+
+ if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0))
+ hang();
+ } else {
+ socfpga_s2f_bridges_reset(enable);
+
+ }
+}
+
+void __secure socfpga_bridges_reset_psci(int enable)
+{
+ socfpga_s2f_bridges_reset(enable);
}
/*
--
2.26.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 4/5] arm: socfpga: soc64: Add f2s bridge support
2022-11-13 14:57 [PATCH 1/5] arm: socfpga: Add F2SDRAM_MANAGER base address Jit Loon Lim
2022-11-13 14:57 ` [PATCH 2/5] arm: socfpga: soc64: Update reset manager registers Jit Loon Lim
2022-11-13 14:57 ` [PATCH 3/5] arm: socfpga: soc64: Move bridges reset to common function Jit Loon Lim
@ 2022-11-13 14:57 ` Jit Loon Lim
2022-11-13 14:57 ` [PATCH 5/5] arm: socfpga: soc64: Avoid hang in bridge reset Jit Loon Lim
3 siblings, 0 replies; 5+ messages in thread
From: Jit Loon Lim @ 2022-11-13 14:57 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang, Ley Foon Tan
From: Ley Foon Tan <ley.foon.tan@intel.com>
HSD #1508586908-5: Add F2H and F2SDRAM bridges disable/enable support, based on software
programming flow in HW documentation.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/reset_manager_s10.c | 122 +++++++++++++++++++++-
1 file changed, 121 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 20ab374881..690cfb2b20 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -17,6 +17,57 @@
DECLARE_GLOBAL_DATA_PTR;
+/* F2S manager registers */
+#define F2SDRAM_SIDEBAND_FLAGINSTATUS0 0x14
+#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50
+#define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54
+
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+#define FLAGINSTATUS0_MPFE_NOC_IDLE (BIT(0) | BIT(4) | BIT(8))
+#define FLAGINSTATUS0_MPFE_NOC_IDLEACK (BIT(1) | BIT(5) | BIT(9))
+#define FLAGINSTATUS0_F2S_CMD_EMPTY (BIT(2) | BIT(6) | BIT(10))
+#define FLAGINSTATUS0_F2S_RESP_EMPTY (BIT(3) | BIT(7) | BIT(11))
+
+#define FLGAOUTSET0_MPFE_NOC_IDLEREQ (BIT(0) | BIT(3) | BIT(6))
+#define FLGAOUTSET0_F2S_EN (BIT(1) | BIT(4) | BIT(7))
+#define FLGAOUTSET0_F2S_FORCE_DRAIN (BIT(2) | BIT(5) | BIT(8))
+
+#define FLGAOUTCLR0_F2S_IDLEREQ (BIT(0) | BIT(3) | BIT(6))
+#else
+#define FLAGINSTATUS0_MPFE_NOC_IDLE BIT(0)
+#define FLAGINSTATUS0_MPFE_NOC_IDLEACK BIT(1)
+#define FLAGINSTATUS0_F2S_CMD_EMPTY BIT(2)
+#define FLAGINSTATUS0_F2S_RESP_EMPTY BIT(3)
+
+#define FLGAOUTSET0_MPFE_NOC_IDLEREQ BIT(0)
+#define FLGAOUTSET0_F2S_EN BIT(1)
+#define FLGAOUTSET0_F2S_FORCE_DRAIN BIT(2)
+
+#define FLGAOUTCLR0_F2S_IDLEREQ BIT(0)
+#endif
+
+#define POLL_FOR_ZERO(expr, timeout_ms) \
+ { \
+ int timeout = (timeout_ms); \
+ while ((expr)) { \
+ if (!timeout) \
+ break; \
+ timeout--; \
+ __socfpga_udelay(1000); \
+ } \
+ }
+
+#define POLL_FOR_SET(expr, timeout_ms) \
+ { \
+ int timeout = (timeout_ms); \
+ while (!(expr)) { \
+ if (!timeout) \
+ break; \
+ timeout--; \
+ __socfpga_udelay(1000); \
+ } \
+ }
+
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
@@ -57,6 +108,74 @@ void socfpga_per_reset_all(void)
writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
}
+static __always_inline void socfpga_f2s_bridges_reset(int enable)
+{
+ int timeout_ms = 300;
+ u32 empty;
+
+ if (enable) {
+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+ BRGMODRST_FPGA2SOC_BRIDGES);
+ clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0,
+ FLGAOUTSET0_MPFE_NOC_IDLEREQ);
+
+ POLL_FOR_ZERO((readl(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGINSTATUS0) &
+ FLAGINSTATUS0_MPFE_NOC_IDLEACK), timeout_ms);
+ clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0,
+ FLGAOUTSET0_F2S_FORCE_DRAIN);
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN);
+
+ __socfpga_udelay(1); /* wait 1us */
+ } else {
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKEN,
+ RSTMGR_HDSKEN_FPGAHSEN);
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ,
+ RSTMGR_HDSKREQ_FPGAHSREQ);
+ POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() +
+ RSTMGR_SOC64_HDSKACK), timeout_ms);
+ clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN);
+ __socfpga_udelay(1);
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTSET0,
+ FLGAOUTSET0_F2S_FORCE_DRAIN);
+ __socfpga_udelay(1);
+
+ do {
+ /*
+ * Read response queue status twice to ensure it is
+ * empty.
+ */
+ empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGINSTATUS0) &
+ FLAGINSTATUS0_F2S_RESP_EMPTY;
+ if (empty) {
+ empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGINSTATUS0) &
+ FLAGINSTATUS0_F2S_RESP_EMPTY;
+ if (empty)
+ break;
+ }
+
+ timeout_ms--;
+ __socfpga_udelay(1000);
+ } while (timeout_ms);
+
+ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
+ BRGMODRST_FPGA2SOC_BRIDGES &
+ ~RSTMGR_BRGMODRST_FPGA2SOC_MASK);
+ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ,
+ RSTMGR_HDSKREQ_FPGAHSREQ);
+ setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS +
+ F2SDRAM_SIDEBAND_FLAGOUTCLR0,
+ FLGAOUTCLR0_F2S_IDLEREQ);
+ }
+}
+
static __always_inline void socfpga_s2f_bridges_reset(int enable)
{
if (enable) {
@@ -109,13 +228,14 @@ void socfpga_bridges_reset(int enable)
hang();
} else {
socfpga_s2f_bridges_reset(enable);
-
+ socfpga_f2s_bridges_reset(enable);
}
}
void __secure socfpga_bridges_reset_psci(int enable)
{
socfpga_s2f_bridges_reset(enable);
+ socfpga_f2s_bridges_reset(enable);
}
/*
--
2.26.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 5/5] arm: socfpga: soc64: Avoid hang in bridge reset
2022-11-13 14:57 [PATCH 1/5] arm: socfpga: Add F2SDRAM_MANAGER base address Jit Loon Lim
` (2 preceding siblings ...)
2022-11-13 14:57 ` [PATCH 4/5] arm: socfpga: soc64: Add f2s bridge support Jit Loon Lim
@ 2022-11-13 14:57 ` Jit Loon Lim
3 siblings, 0 replies; 5+ messages in thread
From: Jit Loon Lim @ 2022-11-13 14:57 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang, Ley Foon Tan
From: Ley Foon Tan <ley.foon.tan@intel.com>
HSD #1508586908-6: Software shouldn't hang the system if the HPS bridge reset is failed.
Change hang() to error message.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
.../include/mach/base_addr_soc64.h | 1 +
arch/arm/mach-socfpga/include/mach/timer.h | 31 +++++++++++++++++++
arch/arm/mach-socfpga/reset_manager_s10.c | 12 +++++--
3 files changed, 41 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 3f899fcfa3..c0de59f279 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -16,6 +16,7 @@
#else
#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
#endif
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000
#define SOCFPGA_SMMU_ADDRESS 0xfa000000
#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
diff --git a/arch/arm/mach-socfpga/include/mach/timer.h b/arch/arm/mach-socfpga/include/mach/timer.h
index 82596e412e..be56b4968f 100644
--- a/arch/arm/mach-socfpga/include/mach/timer.h
+++ b/arch/arm/mach-socfpga/include/mach/timer.h
@@ -6,6 +6,9 @@
#ifndef _SOCFPGA_TIMER_H_
#define _SOCFPGA_TIMER_H_
+#include <asm/barriers.h>
+#include <div64.h>
+
struct socfpga_timer {
u32 load_val;
u32 curr_val;
@@ -14,4 +17,32 @@ struct socfpga_timer {
u32 int_stat;
};
+static __always_inline u64 __socfpga_get_time_stamp(void)
+{
+ u64 cntpct;
+
+ isb();
+ asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+ return cntpct;
+}
+
+static __always_inline u64 __socfpga_usec_to_tick(u64 usec)
+{
+ u64 tick = usec;
+ u64 cntfrq;
+
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
+ tick *= cntfrq;
+ do_div(tick, 1000000);
+ return tick;
+}
+
+static __always_inline void __socfpga_udelay(u64 usec)
+{
+ u64 tmp = __socfpga_get_time_stamp() + __socfpga_usec_to_tick(usec);
+
+ while (__socfpga_get_time_stamp() < tmp + 1)
+ ;
+}
+
#endif
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 690cfb2b20..0274c4dbdb 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -8,13 +8,15 @@
#include <hang.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <asm/secure.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/smc_api.h>
#include <asm/arch/system_manager.h>
+#include <asm/arch/timer.h>
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+#include <exports.h>
#include <linux/iopoll.h>
#include <linux/intel-smc.h>
-
DECLARE_GLOBAL_DATA_PTR;
/* F2S manager registers */
@@ -223,9 +225,13 @@ void socfpga_bridges_reset(int enable)
{
if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
u64 arg = enable;
+ int ret;
- if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0))
- hang();
+ ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL,
+ 0);
+ if (ret)
+ printf("Failed to %s the HPS bridges, error %d\n",
+ enable ? "enable" : "disable", ret);
} else {
socfpga_s2f_bridges_reset(enable);
socfpga_f2s_bridges_reset(enable);
--
2.26.2
^ permalink raw reply related [flat|nested] 5+ messages in thread