From: Jit Loon Lim <jit.loon.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>,
Vignesh R <vigneshr@ti.com>, Marek <marex@denx.de>,
Simon <simon.k.r.goldschmidt@gmail.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Siew Chin <elly.siew.chin.lim@intel.com>,
Sin Hui <sin.hui.kho@intel.com>, Raaj <raaj.lokanathan@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>
Subject: [PATCH 1/2] drivers: watchdog: Enhance watchdog support in SPL for Stratix 10 and Agilex
Date: Tue, 22 Nov 2022 22:18:36 +0800 [thread overview]
Message-ID: <20221122141837.24055-1-jit.loon.lim@intel.com> (raw)
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Change watchdog default timeout to 10 seconds and enable watchdog before
initializing other component (example: DDR). Thus, watchdog need to be
fully executed in onchip ram.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/spl_agilex.c | 17 +++++++++--------
arch/arm/mach-socfpga/spl_s10.c | 14 +++++++-------
drivers/watchdog/Kconfig | 2 +-
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index ee5a9dc1e2..c279f97cea 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -20,7 +20,7 @@
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-#include <watchdog.h>
+#include <wdt.h>
#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,13 +40,6 @@ void board_init_f(ulong dummy)
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
-#ifdef CONFIG_HW_WATCHDOG
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
-#endif
-
/* ensure all processors are not released prior Linux boot */
writeq(0, CPU_RELEASE_ADDR);
@@ -60,6 +53,14 @@ void board_init_f(ulong dummy)
hang();
}
+ /*
+ * Enable watchdog as early as possible before initializing other
+ * component. Watchdog need to be enabled after clock driver because
+ * it will retrieve the clock frequency from clock driver.
+ */
+ if (CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
+
preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index c20e87cdbe..4044dc335e 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -21,7 +21,7 @@
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-#include <watchdog.h>
+#include <wdt.h>
#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -41,12 +41,12 @@ void board_init_f(ulong dummy)
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
-#ifdef CONFIG_HW_WATCHDOG
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
-#endif
+ /*
+ * Enable watchdog as early as possible before initializing other
+ * component.
+ */
+ if (CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
/* ensure all processors are not released prior Linux boot */
writeq(0, CPU_RELEASE_ADDR);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 50e6a1efba..a6c242ac9d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -27,7 +27,7 @@ config WATCHDOG_TIMEOUT_MSECS
int "Watchdog timeout in msec"
default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
default 128000 if ARCH_MX7 || ARCH_VF610
- default 30000 if ARCH_SOCFPGA
+ default 10000 if ARCH_SOCFPGA
default 16000 if ARCH_SUNXI
default 60000
help
--
2.26.2
next reply other threads:[~2022-11-22 14:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-22 14:18 Jit Loon Lim [this message]
2022-11-22 14:18 ` [PATCH 2/2] drivers: watchdog: Enhance watchdog support in SPL for N5X Jit Loon Lim
2022-12-05 12:27 ` [PATCH 1/2] drivers: watchdog: Enhance watchdog support in SPL for Stratix 10 and Agilex Stefan Roese
2022-12-05 13:27 ` Lim, Jit Loon
2023-01-18 6:54 ` Stefan Roese
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221122141837.24055-1-jit.loon.lim@intel.com \
--to=jit.loon.lim@intel.com \
--cc=alif.zakuan.yuslaimi@intel.com \
--cc=boon.khai.ng@intel.com \
--cc=dinesh.maniyam@intel.com \
--cc=elly.siew.chin.lim@intel.com \
--cc=jagan@amarulasolutions.com \
--cc=kok.kiang.hea@intel.com \
--cc=marex@denx.de \
--cc=muhammad.hazim.izzat.zamri@intel.com \
--cc=raaj.lokanathan@intel.com \
--cc=sieu.mun.tang@intel.com \
--cc=simon.k.r.goldschmidt@gmail.com \
--cc=sin.hui.kho@intel.com \
--cc=teik.heng.chong@intel.com \
--cc=tien.fong.chee@intel.com \
--cc=u-boot@lists.denx.de \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox