[PATCH] drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration

[PATCH] drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration

[Jit Loon Lim]

From: Yau Wai Gan <yau.wai.gan@intel.com>

FPGA configuration encounter failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.

Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
 drivers/fpga/intel_sdm_mb.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index f5fd9a14c2..72958aac86 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -9,6 +9,8 @@
 #include <watchdog.h>
 #include <asm/arch/mailbox_s10.h>
 #include <asm/arch/smc_api.h>
+#include <asm/cache.h>
+#include <cpu_func.h>
 #include <linux/delay.h>
 #include <linux/intel-smc.h>
 
@@ -121,6 +123,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	debug("Invoking FPGA_CONFIG_START...\n");
 
+	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
+
 	ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
 
 	if (ret) {
@@ -394,6 +398,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	u32 resp_len = 2;
 	u32 resp_buf[2];
 
+	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
+
 	debug("Sending MBOX_RECONFIG...\n");
 	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
 			    NULL, 0, &resp_len, resp_buf);
-- 
2.26.2

[PATCH] drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration

[Naresh Kumar Ravulapalli]

FPGA configuration encounters failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
---
 drivers/fpga/intel_sdm_mb.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 5fe4dbdfd32..a2f3b160a73 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include <altera.h>
@@ -9,6 +10,8 @@
 #include <watchdog.h>
 #include <asm/arch/mailbox_s10.h>
 #include <asm/arch/smc_api.h>
+#include <asm/cache.h>
+#include <cpu_func.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/intel-smc.h>
@@ -738,6 +741,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	debug("Invoking FPGA_CONFIG_START...\n");
 
+	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
+
 	ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
 
 	if (ret) {
@@ -1023,6 +1028,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	u32 resp_len = 2;
 	u32 resp_buf[2];
 
+	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
+
 	debug("Sending MBOX_RECONFIG...\n");
 	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
 			    NULL, 0, &resp_len, resp_buf);
-- 
2.35.3

Re: [PATCH] drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration

[Michal Simek]

On 5/6/25 03:28, Naresh Kumar Ravulapalli wrote:
> FPGA configuration encounters failure when the cache is not flushed.
> Add cache flushing to the memory region that holds the FPGA
> configuration bitstream.
> 
> Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
> ---
>   drivers/fpga/intel_sdm_mb.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
> index 5fe4dbdfd32..a2f3b160a73 100644
> --- a/drivers/fpga/intel_sdm_mb.c
> +++ b/drivers/fpga/intel_sdm_mb.c
> @@ -1,6 +1,7 @@
>   // SPDX-License-Identifier: GPL-2.0+
>   /*
>    * Copyright (C) 2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2025 Altera Corporation <www.altera.com>
>    */
>   
>   #include <altera.h>
> @@ -9,6 +10,8 @@
>   #include <watchdog.h>
>   #include <asm/arch/mailbox_s10.h>
>   #include <asm/arch/smc_api.h>
> +#include <asm/cache.h>
> +#include <cpu_func.h>
>   #include <linux/delay.h>
>   #include <linux/errno.h>
>   #include <linux/intel-smc.h>
> @@ -738,6 +741,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
>   
>   	debug("Invoking FPGA_CONFIG_START...\n");
>   
> +	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
> +
>   	ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
>   
>   	if (ret) {
> @@ -1023,6 +1028,8 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
>   	u32 resp_len = 2;
>   	u32 resp_buf[2];
>   
> +	flush_dcache_range((unsigned long)rbf_data, (unsigned long)(rbf_data + rbf_size));
> +
>   	debug("Sending MBOX_RECONFIG...\n");
>   	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
>   			    NULL, 0, &resp_len, resp_buf);

Applied.
M