* [PATCH] arm: socfpga: n5x: Enables mailbox functionality for QSPI before DDR
@ 2022-11-22 15:01 Jit Loon Lim
0 siblings, 0 replies; only message in thread
From: Jit Loon Lim @ 2022-11-22 15:01 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Vignesh R, Marek, Simon, Tien Fong, Kok Kiang,
Siew Chin, Sin Hui, Raaj, Dinesh, Boon Khai, Alif, Teik Heng,
Hazim, Jit Loon Lim, Sieu Mun Tang
From: Tien Fong Chee <tien.fong.chee@intel.com>
Enables mailbox functionality for QSPI before initializing DDR, because
storing calibration data into QSPI is required when DDR retention is
enabled.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
arch/arm/mach-socfpga/spl_n5x.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c
index c56b5a1b88..92037190e2 100644
--- a/arch/arm/mach-socfpga/spl_n5x.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -81,6 +81,12 @@ void board_init_f(ulong dummy)
hang();
}
+ mbox_init();
+
+#if IS_ENABLED(CONFIG_CADENCE_QSPI)
+ mbox_qspi_open();
+#endif
+
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
@@ -88,10 +94,4 @@ void board_init_f(ulong dummy)
hang();
}
#endif
-
- mbox_init();
-
-#ifdef CONFIG_CADENCE_QSPI
- mbox_qspi_open();
-#endif
}
--
2.26.2
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2022-11-22 15:01 [PATCH] arm: socfpga: n5x: Enables mailbox functionality for QSPI before DDR Jit Loon Lim
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