From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8036C4332F for ; Wed, 23 Nov 2022 14:08:12 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9DFE9852CC; Wed, 23 Nov 2022 15:08:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cy31TcEH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4B471851CB; Wed, 23 Nov 2022 15:07:57 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8A18F8521B for ; Wed, 23 Nov 2022 15:07:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669212474; x=1700748474; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jnsycXsWaLK/UeOX2UrCc0YPHDj3GM0CCOI7kBNY+Is=; b=cy31TcEHdgEnWD4tMZq28D0bsrnpNnw/EjVreXaKIC5g4xNtrCRxukFg xPIk982LLFSGUmLVTEXT75kj+0RtZNoVuYxAsquuiYUO7leTQ3B1b8ilR BNqYAZmdZcbMMnpGkZITdAaOp1iZ8XHebNJ63SaEX+BvJoFgpEAJkn2Tk u1uRJho4Vvotk2vUG5S6nZ/YkM22FnrS2Wyossm/FjK50wndingFQnkSG mkG4rXvo0RGXp1oyQK1i6vwKQsarxI5ih/KFsgNYBIKR8zAn9hYw7ly3V shFFSG+l8rijPOuf+MfS2sBxMTEGZRpuQ8cyDqxWJjAXYe/mB3gQyR2qk w==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="400364709" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="400364709" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 06:07:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="641808328" X-IronPort-AV: E=Sophos;i="5.96,187,1665471600"; d="scan'208";a="641808328" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga002.jf.intel.com with ESMTP; 23 Nov 2022 06:07:22 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 5466A482F; Wed, 23 Nov 2022 22:07:22 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 52702E0095B; Wed, 23 Nov 2022 22:07:22 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang , Ley Foon Tan Subject: [PATCH 2/2] arm: socfpga: soc64: Add mask support to INTEL_SIP_SMC_HPS_SET_BRIDGES Date: Wed, 23 Nov 2022 22:07:20 +0800 Message-Id: <20221123140720.31941-2-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20221123140720.31941-1-jit.loon.lim@intel.com> References: <20221123140720.31941-1-jit.loon.lim@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Ley Foon Tan HSD #18016042797-2: Add mask support to INTEL_SIP_SMC_HPS_SET_BRIDGES SMC call. Signed-off-by: Ley Foon Tan Signed-off-by: Jit Loon Lim --- arch/arm/mach-socfpga/reset_manager_s10.c | 10 +++++++--- include/linux/intel-smc.h | 14 ++++++++++---- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 128cdbbbe3..bc643218d2 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -266,11 +266,15 @@ static __always_inline void socfpga_s2f_bridges_reset(int enable, void socfpga_bridges_reset(int enable, unsigned int mask) { if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { - u64 arg = enable; + u64 arg[2]; int ret; - ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, - 0); + /* Set bit-1 to indicate has mask value in arg[1]. */ + arg[0] = (enable & BIT(0)) | BIT(1); + arg[1] = mask; + + ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, arg, + ARRAY_SIZE(arg), NULL, 0); if (ret) printf("Failed to %s the HPS bridges, error %d\n", enable ? "enable" : "disable", ret); diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index a54eff43ad..e15fa3d4da 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -482,10 +482,16 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * Call register usage: * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES * a1 Set bridges status: - * 0 - Disable - * 1 - Enable - * a2-7 not used - * + * Bit 0: 0 - Disable, 1 - Enable + * Bit 1: 1 - Has mask value in a2 + * a2 Mask value + * Bit 0: soc2fpga + * Bit 1: lwhps2fpga + * Bit 2: fpga2soc + * Bit 3: f2sdram0 (For Stratix 10 only) + * Bit 4: f2sdram1 (For Stratix 10 only) + * Bit 5: f2sdram2 (For Stratix 10 only) + * a3-7 not used * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ -- 2.26.2