From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52B9EC4332F for ; Thu, 24 Nov 2022 03:16:39 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2DA39855EE; Thu, 24 Nov 2022 04:16:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MIEpP9Y7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 92E8A855F1; Thu, 24 Nov 2022 04:16:35 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9E3F2855ED for ; Thu, 24 Nov 2022 04:16:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=jitloonl@ecsmtp.png.intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669259792; x=1700795792; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6QOasw01KAZlrx9eJKNhnNbrgAWm8ha3bcY0SzOydfs=; b=MIEpP9Y7cC4njIJYYRj/SbkWy9zq+vfNcBn5mBIgSuUJNop/i77sTNgq Ai1vp/2rAk7JZhysx//klIhNqiqOKtlHC8Jky+vnMXtGtzZNKX9lybse3 43miZC6JPWcU1WJ9ksVEs5ycLniZZjQeMpIKxidOrBcTXqxoMiqOcA4M6 vpmR642gmbYCfpfF5CNYC389aPVdnLe33Tty0Bhx/SmpxRF6W2ymopMBe MytiQ1uMiL6qQi0zgQacSdFNKLqmwykQItUo0D5CI8q/uD3h98yPcv+5M HK5R0HKzirtPMb19RjDaMWCSjssqUHIWWePsEr9c1EHHFHP7tAcqeZtlp w==; X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="378464935" X-IronPort-AV: E=Sophos;i="5.96,189,1665471600"; d="scan'208";a="378464935" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2022 19:16:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10540"; a="816698931" X-IronPort-AV: E=Sophos;i="5.96,189,1665471600"; d="scan'208";a="816698931" Received: from pglmail07.png.intel.com ([10.221.193.207]) by orsmga005.jf.intel.com with ESMTP; 23 Nov 2022 19:16:23 -0800 Received: from localhost (pgli0028.png.intel.com [10.221.84.177]) by pglmail07.png.intel.com (Postfix) with ESMTP id 6C14D4832; Thu, 24 Nov 2022 11:16:22 +0800 (+08) Received: by localhost (Postfix, from userid 12048045) id 56381E00959; Thu, 24 Nov 2022 11:16:22 +0800 (+08) From: Jit Loon Lim To: u-boot@lists.denx.de Cc: Jagan Teki , Vignesh R , Marek , Simon , Tien Fong , Kok Kiang , Siew Chin , Sin Hui , Raaj , Dinesh , Boon Khai , Alif , Teik Heng , Hazim , Jit Loon Lim , Sieu Mun Tang Subject: [PATCH] ddr: altera: n5x: Fixing debug log typo Date: Thu, 24 Nov 2022 11:16:20 +0800 Message-Id: <20221124031620.23784-1-jit.loon.lim@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Fixing debug log typo. Signed-off-by: Tien Fong Chee Signed-off-by: Jit Loon Lim --- drivers/ddr/altera/sdram_n5x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 8a5f0a3df4..b4d52f7ac2 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2345,7 +2345,7 @@ static void set_cal_res_to_rankctrl(u32 reg_addr, u16 update_value, debug("max value divided by 2 is 0x%x\n", update_value); debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg); - debug("update with train result\n"); + debug("updating with train result\n"); value = (reg & mask) >> shift; @@ -2365,8 +2365,8 @@ static void set_cal_res_to_rankctrl(u32 reg_addr, u16 update_value, writel((reg & (~mask)) | value, (uintptr_t)reg_addr); reg = readl((uintptr_t)reg_addr); - debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg); - debug("update with train result\n"); + debug("umclt2 register 0x%x value is 0%x after ", reg_addr, reg); + debug("updating with train result\n"); } /* helper function for updating train result to register */ @@ -2379,7 +2379,7 @@ static void set_cal_res_to_reg(u32 reg_addr, u16 update_value, u32 mask, debug("max value divided by 2 is 0x%x\n", update_value); debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg); - debug("update with train result\n"); + debug("updating with train result\n"); value = (reg & mask) >> shift; @@ -2389,8 +2389,8 @@ static void set_cal_res_to_reg(u32 reg_addr, u16 update_value, u32 mask, writel((reg & (~mask)) | value, (uintptr_t)reg_addr); reg = readl((uintptr_t)reg_addr); - debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg); - debug("update with train result\n"); + debug("umclt2 register 0x%x value is 0%x after ", reg_addr, reg); + debug("updating with train result\n"); } static u16 get_max_txdqsdlytg0_ux_p0(struct ddr_handoff *handoff, u32 reg, -- 2.26.2