[PoC 239/241] global: Migrate CONFIG_X86_REFCODE_ADDR to CFG

Tom Rini
2022-11-20T14:28:59Z

arch/x86/cpu/broadwell/refcode.c | 2 +-
arch/x86/dts/u-boot.dtsi | 2 +-
include/configs/x86-chromebook.h | 2 +-
scripts/config_whitelist.txt | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c
index 94c2e05346a6..3b7ec2b74e8e 100644
--- a/arch/x86/cpu/broadwell/refcode.c
+++ b/arch/x86/cpu/broadwell/refcode.c
@@ -78,7 +78,7 @@ static int cpu_run_reference_code(void)
int ret, dummy;
int size;

- hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR;
+ hdr = (struct rmodule_header *)CFG_X86_REFCODE_ADDR;
debug("Extracting code from rmodule at %p\n", hdr);
if (hdr->magic != RMODULE_MAGIC) {
debug("Invalid rmodule magic\n");
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 454efc17614e..e0de33180910 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -149,7 +149,7 @@
#endif
#ifdef CONFIG_HAVE_REFCODE
intel-refcode {
- offset = <CONFIG_X86_REFCODE_ADDR>;
+ offset = <CFG_X86_REFCODE_ADDR>;
};
#endif
#ifdef CONFIG_TPL
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 7d93dcbfc2e5..fa45bf809700 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -7,7 +7,7 @@
#define _X86_CHROMEBOOK_H

#define CFG_X86_MRC_ADDR 0xfffa0000
-#define CONFIG_X86_REFCODE_ADDR 0xffea0000
+#define CFG_X86_REFCODE_ADDR 0xffea0000
#define CONFIG_X86_REFCODE_RUN_ADDR 0

#define VIDEO_IO_OFFSET 0
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 66173404901d..2895dd09bfcf 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -254,5 +254,5 @@ CFG_WATCHDOG_PRESC
CFG_WATCHDOG_RC
CFG_X86EMU_RAW_IO
CFG_X86_MRC_ADDR
-CONFIG_X86_REFCODE_ADDR
+CFG_X86_REFCODE_ADDR
CONFIG_X86_REFCODE_RUN_ADDR
--
2.25.1