[PATCH 032/149] global: Migrate CONFIG_FPGA_DELAY to CFG

Tom Rini
2022-12-04T15:12:17Z

Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY

Signed-off-by: Tom Rini <trini@konsulko.com>
---
README | 2 +-
drivers/fpga/ACEX1K.c | 22 ++++++++++-----------
drivers/fpga/cyclon2.c | 12 ++++++------
drivers/fpga/spartan2.c | 42 ++++++++++++++++++++---------------------
drivers/fpga/spartan3.c | 42 ++++++++++++++++++++---------------------
drivers/fpga/virtex2.c | 24 +++++++++++------------
6 files changed, 72 insertions(+), 72 deletions(-)

diff --git a/README b/README
index a278825bbcc9..84086764d810 100644
--- a/README
+++ b/README
@@ -1018,7 +1018,7 @@ The following options need to be configured:
will require a board or device specific function to
be written.

- CONFIG_FPGA_DELAY
+ CFG_FPGA_DELAY

If defined, a function that provides delays in the FPGA
configuration driver.
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c
index ca49ee40a71d..4c00cdf0b57d 100644
--- a/drivers/fpga/ACEX1K.c
+++ b/drivers/fpga/ACEX1K.c
@@ -17,11 +17,11 @@

/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif

#ifndef CFG_SYS_FPGA_WAIT
@@ -137,7 +137,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
/* Wait for nSTATUS to be released (i.e. deasserted) */
ts = get_timer (0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
@@ -147,7 +147,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
} while ((*fn->status) (cookie));

/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();

/* Load the data */
while (bytecount < bsize) {
@@ -172,13 +172,13 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
do {
/* Deassert the clock */
(*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Write data */
(*fn->data) ((val & 0x01), true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (true, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
val >>= 1;
i --;
} while (i > 0);
@@ -189,7 +189,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
#endif
}

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc (' '); /* terminate the dotted line */
@@ -210,9 +210,9 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
*/

for (i = 0; i < 12; i++) {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
}

diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index 3eed461e1e5c..6e8a313db35b 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -15,11 +15,11 @@

/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif

#ifndef CFG_SYS_FPGA_WAIT
@@ -129,7 +129,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
/* Wait for nSTATUS to be asserted */
ts = get_timer(0); /* get current time */
do {
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
/* check the time */
puts("** Timeout waiting for STATUS to go high.\n");
@@ -139,7 +139,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
} while (!(*fn->status) (cookie));

/* Get ready for the burn */
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();

ret = (*fn->write) (buf, bsize, true, cookie);
if (ret) {
@@ -151,7 +151,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
puts(" OK? ...");
#endif

- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc(' '); /* terminate the dotted line */
diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 68971d934702..6eef87b78e16 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -12,11 +12,11 @@

/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif

#ifndef CFG_SYS_FPGA_WAIT
@@ -140,13 +140,13 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
(*fn->pgm) (true, true, cookie); /* Assert the program, commit */

/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */

ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
@@ -164,9 +164,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - Check the error bit? */

(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -175,9 +175,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -194,7 +194,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
}

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->cs) (false, true, cookie); /* Deassert the chip select */
(*fn->wr) (false, true, cookie); /* Deassert the write pin */

@@ -207,9 +207,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
ret_val = FPGA_SUCCESS;
while ((*fn->done) (cookie) == FPGA_FAIL) {

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -330,7 +330,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
return FPGA_FAIL;
@@ -338,13 +338,13 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
} while (!(*fn->init) (cookie));

/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */

ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
@@ -365,13 +365,13 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
do {
/* Deassert the clock */
(*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val & 0x80), true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (true, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
@@ -382,7 +382,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
}

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
@@ -395,9 +395,9 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)

while (! (*fn->done) (cookie)) {

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

putc ('*');
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 1d5073cb59d4..e892fa571f19 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -17,11 +17,11 @@

/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
- * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * If there is a need to operate slower, define CFG_FPGA_DELAY in
* the board config file to slow things down.
*/
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif

#ifndef CFG_SYS_FPGA_WAIT
@@ -145,13 +145,13 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
(*fn->pgm) (true, true, cookie); /* Assert the program, commit */

/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */

ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
@@ -169,9 +169,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - Check the error bit? */

(*fn->wdata) (data[bytecount++], true, cookie); /* write the data */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -180,9 +180,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -199,7 +199,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
}

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->cs) (false, true, cookie); /* Deassert the chip select */
(*fn->wr) (false, true, cookie); /* Deassert the write pin */

@@ -214,9 +214,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
@@ -337,7 +337,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
if (*fn->abort)
@@ -347,13 +347,13 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
} while (!(*fn->init) (cookie));

/* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->pgm) (false, true, cookie); /* Deassert the program, commit */

ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
if (*fn->abort)
@@ -381,13 +381,13 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
do {
/* Deassert the clock */
(*fn->clk) (false, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val & 0x80), true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (true, true, cookie);
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
@@ -399,7 +399,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
}
}

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
@@ -414,9 +414,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */

- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (false, true, cookie); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
+ CFG_FPGA_DELAY ();
(*fn->clk) (true, true, cookie); /* Assert the clock pin */

putc ('*');
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index ed2a4163f6eb..fc99a5f48314 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -22,13 +22,13 @@

/*
* If the SelectMap interface can be overrun by the processor, enable
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CONFIG_FPGA_DELAY in the board
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
* configuration file and add board-specific support for checking BUSY status.
* By default, assume that the SelectMap interface cannot be overrun.
*/

-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
#endif

/*
@@ -196,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
} while (!(*fn->init)(cookie));

(*fn->pgm)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (fn->clk)
(*fn->clk)(true, true, cookie);

@@ -205,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
*/
ts = get_timer(0);
do {
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
__func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
@@ -233,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
/*
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
*/
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
if (fn->cs)
(*fn->cs)(false, true, cookie);
if (fn->wr)
@@ -269,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
(*fn->wbulkdata)(&dummy, 1, true, cookie);
} else {
(*fn->wdata)(0xff, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
}
}
@@ -335,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif

(*fn->wdata)(data[bytecount++], true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();

/*
* Cycle the clock pin
*/
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);

#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -472,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
for (bit = 7; bit >= 0; --bit) {
unsigned char curr_bit = (curr_data >> bit) & 1;
(*fn->wdata)(curr_bit, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(false, true, cookie);
- CONFIG_FPGA_DELAY();
+ CFG_FPGA_DELAY();
(*fn->clk)(true, true, cookie);
}

--
2.25.1