From: Jit Loon Lim <jit.loon.lim@intel.com>
To: u-boot@lists.denx.de
Cc: Jagan Teki <jagan@amarulasolutions.com>,
Vignesh R <vigneshr@ti.com>, Marek <marex@denx.de>,
Simon <simon.k.r.goldschmidt@gmail.com>,
Tien Fong <tien.fong.chee@intel.com>,
Kok Kiang <kok.kiang.hea@intel.com>,
Siew Chin <elly.siew.chin.lim@intel.com>,
Sin Hui <sin.hui.kho@intel.com>, Raaj <raaj.lokanathan@intel.com>,
Dinesh <dinesh.maniyam@intel.com>,
Boon Khai <boon.khai.ng@intel.com>,
Alif <alif.zakuan.yuslaimi@intel.com>,
Teik Heng <teik.heng.chong@intel.com>,
Hazim <muhammad.hazim.izzat.zamri@intel.com>,
Jit Loon Lim <jit.loon.lim@intel.com>,
Sieu Mun Tang <sieu.mun.tang@intel.com>
Subject: [PATCH] ddr: altera: n5x: Fixing debug log typo
Date: Sun, 4 Dec 2022 22:31:01 +0800 [thread overview]
Message-ID: <20221204143101.8031-1-jit.loon.lim@intel.com> (raw)
From: Tien Fong Chee <tien.fong.chee@intel.com>
Fixing debug log typo.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
---
drivers/ddr/altera/sdram_n5x.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
index 8a5f0a3df4..b4d52f7ac2 100644
--- a/drivers/ddr/altera/sdram_n5x.c
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -2345,7 +2345,7 @@ static void set_cal_res_to_rankctrl(u32 reg_addr, u16 update_value,
debug("max value divided by 2 is 0x%x\n", update_value);
debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
- debug("update with train result\n");
+ debug("updating with train result\n");
value = (reg & mask) >> shift;
@@ -2365,8 +2365,8 @@ static void set_cal_res_to_rankctrl(u32 reg_addr, u16 update_value,
writel((reg & (~mask)) | value, (uintptr_t)reg_addr);
reg = readl((uintptr_t)reg_addr);
- debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
- debug("update with train result\n");
+ debug("umclt2 register 0x%x value is 0%x after ", reg_addr, reg);
+ debug("updating with train result\n");
}
/* helper function for updating train result to register */
@@ -2379,7 +2379,7 @@ static void set_cal_res_to_reg(u32 reg_addr, u16 update_value, u32 mask,
debug("max value divided by 2 is 0x%x\n", update_value);
debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
- debug("update with train result\n");
+ debug("updating with train result\n");
value = (reg & mask) >> shift;
@@ -2389,8 +2389,8 @@ static void set_cal_res_to_reg(u32 reg_addr, u16 update_value, u32 mask,
writel((reg & (~mask)) | value, (uintptr_t)reg_addr);
reg = readl((uintptr_t)reg_addr);
- debug("umclt2 register 0x%x value is 0%x before ", reg_addr, reg);
- debug("update with train result\n");
+ debug("umclt2 register 0x%x value is 0%x after ", reg_addr, reg);
+ debug("updating with train result\n");
}
static u16 get_max_txdqsdlytg0_ux_p0(struct ddr_handoff *handoff, u32 reg,
--
2.26.2
next reply other threads:[~2022-12-04 14:31 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-04 14:31 Jit Loon Lim [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-11-24 3:16 [PATCH] ddr: altera: n5x: Fixing debug log typo Jit Loon Lim
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