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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id o31-20020a056871079f00b00143065d3e99sm12082302oap.5.2022.12.07.03.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 03:42:52 -0800 (PST) From: Kautuk Consul To: Bharat Gooty , Rayagonda Kokatanur , Sean Anderson , Andre Przywara , Simon Glass , Ilias Apalodimas , Philippe Reynes , Sughosh Ganu , Heinrich Schuchardt , Rasmus Villemoes , Eugen Hristev , =?UTF-8?q?Pali=20Roh=C3=A1r?= , Stefan Roese , Minkyu Kang , Loic Poulain , u-boot@lists.denx.de, ycliang@andestech.com, bmeng.cn@gmail.com, rickchen36@gmail.com Cc: Kautuk Consul Subject: [PATCH v6 0/3] Add riscv semihosting support in u-boot Date: Wed, 7 Dec 2022 17:12:33 +0530 Message-Id: <20221207114236.2906956-1-kconsul@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v5: - Removed patch 3/3: default enablement of semihosting removed for the qemu-riscv64 targets due to failure of the CI test-cases. This is happening due to the qemu version and some commits currently not taken into qemu latest version. - Added patch 3/3: Added a 3rd patch which adds a dependency on SPL_SEMIHOSTING for the SPL_FS_LOAD_PAYLOAD_NAME config option. This will remove the need for the user to enable any of the SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS config options for SPL_SEMIHOSTING compilations. Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin -semihosting-config enable=on U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 -semihosting-config enable=on Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V common/spl/Kconfig: add dependency on SPL_SEMIHOSTING for SPL payload arch/arm/Kconfig | 46 --------- arch/arm/lib/semihosting.c | 181 +--------------------------------- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 25 +++++ arch/riscv/lib/semihosting.c | 24 +++++ common/spl/Kconfig | 2 +- include/semihosting.h | 11 +++ lib/Kconfig | 47 +++++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++++++++++ 11 files changed, 300 insertions(+), 227 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1