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[2603:6081:7b00:6400:b826:a734:d5f3:47e0]) by smtp.gmail.com with ESMTPSA id n6-20020a5d4006000000b0022cc0a2cbecsm2304897wrp.15.2022.12.09.14.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 14:07:27 -0800 (PST) Date: Fri, 9 Dec 2022 17:07:23 -0500 From: Tom Rini To: Sean Anderson Cc: Rick Chen , ycliang@andestech.com, rickchen36@gmail.com, u-boot@lists.denx.de, sjg@chromium.org, xypron.glpk@gmx.de Subject: Re: [PATCH 1/4] riscv: spl: Introduce SPL_OPENSBI_OS_BOOT Message-ID: <20221209220723.GS3787616@bill-the-cat> References: <20221207062334.21292-1-rick@andestech.com> <1162c5df-dcfc-0908-1d07-32145e3a6aaa@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="QuDWvjWzLL26V8ec" Content-Disposition: inline In-Reply-To: <1162c5df-dcfc-0908-1d07-32145e3a6aaa@gmail.com> X-Clacks-Overhead: GNU Terry Pratchett X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean --QuDWvjWzLL26V8ec Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Dec 09, 2022 at 08:48:37AM -0500, Sean Anderson wrote: > On 12/7/22 01:23, Rick Chen wrote: > > In RISC-V, it only provide normal mode booting currently. > > To speed up the booting process, here provide SPL_OPENSBI_OS_BOOT > > to achieve this feature which will be call Fast-Boot mode. By >=20 > Can you name this something different. We already have something called > fastboot in-tree (the Android-derived protocol) and there's a Microsoft > technology called fastboot (some kind of hibernation). "OS Boot" isn't > very specific either, since we (almost always) boot an OS. Maybe "Eagle > mode" by analogy to Falcon mode, which lets SPL directly boot an OS. >=20 > (Is this substantially different from falcon mode anyway?) I was kind of wondering if this is different, really, from Falcon Mode. Falcon Mode didn't initially have to factor in other-firmware as that's not a hard requirement on arm32 like it is on arm64 or risc-v. But my first read of this was that it seems like the RISC-V specific side of doing Falcon Mode and dealing with the prior stage needs correctly. --=20 Tom --QuDWvjWzLL26V8ec Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmOTsZgACgkQFHw5/5Y0 tyxCFwwAiPDf596OvxqPuuMGcEG+QD7Hohmj8YYzsM5L/6paU3CEyPglgQLa9FP+ 6cp7X5dlHAYa7GpsxT1eQzbKLFijqgjAndKAlHROSkVAG4qTjnE3b+M5SArFuJbE VurypONueEya2RncJE1PwLlm4nCWgubkgYQeRiWsj/AyP2liuZbAc2OObNMxRBQm tP3DgE+FttA53UMRxR7W62r0/vgpnkgK83zF77AItdpG0E9mkbkV52PYxRE4s8fk DB1BalOzvHRUkwC6qhAwzXSf8ELlyMAIkOY7RZWQVu1L0A/mvjjdjPiQ2gX/3y6O yoq7gSwKrYb6pawes+iFkyk6BwGXJOlzFWzakXMTV1fw90HdlGqtrquFmo4AdAyF V7FLAUv3/jRV5KOxzaWwDAn45GoEVBxhv/K+Uxem3X8+RHkMv01+wkq2QdUUmoWi 2NB8rmJSz1xpZYClNY0HBJKJ4J0zh+L4bvoH6GdlbCS9fbL7R260gQG+0+54/Ruu 7kATKGGV =/HE8 -----END PGP SIGNATURE----- --QuDWvjWzLL26V8ec--