Re: [PATCH 8/8] sunxi: Parameterize H616 DRAM code some more

Jernej Škrabec
2022-12-11T18:33:55Z

Dne nedelja, 11. december 2022 ob 17:32:13 CET je Jernej Skrabec napisal(a):
> Part of the code, previously known as "unknown feature" also doesn't
> have constant values. They are derived from TPR0 parameter in vendor
> DRAM code. Introduce that parameter here too, to ease adding new boards.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> ---
> .../include/asm/arch-sunxi/dram_sun50i_h616.h | 1 +
> arch/arm/mach-sunxi/Kconfig | 6 ++++
> arch/arm/mach-sunxi/dram_sun50i_h616.c | 35 +++++++++++++++----
> 3 files changed, 35 insertions(+), 7 deletions(-)

<snip>

> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> b/arch/arm/mach-sunxi/dram_sun50i_h616.c index df06cea42464..6d8f8d371bfe
> 100644
> --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> @@ -808,15 +808,35 @@ static bool mctl_phy_init(struct dram_para *para)
> writel(phy_init[i], &ptr[i]);
>
> if (para->tpr10 & TPR10_UNKNOWN_FEAT0) {
> + if (para->tpr0 & BIT(30))
> + val = (para->tpr0 >> 7) & 0x3e;
> + else
> + val = (para->tpr10 >> 3) & 0x1e;
> +
> ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
> for (i = 0; i < 32; i++)
> - writel(0x16, &ptr[i]);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7a4);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7b8);
> - writel(0x8, SUNXI_DRAM_PHY0_BASE + 0x7d4);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7dc);
> - writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x7e0);
> + writel(val, &ptr[i]);
> +
> + val = (para->tpr10 << 1) & 0x1e;
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7dc);
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
> +
> + /* following configuration is DDR3 specific */
> + val = (para->tpr10 >> 7) & 0x1e;
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7d4);
> + /*
> + * TODO: Offsets 0x79c, 0x794 and 0x7e4 may need
> + * to be set here. However, this doesn't seem to
> + * be needed by any board seen in the wild for now.
> + * It's not implemented because it would unnecessarily
> + * introduce PARA2 and TPR2 options.
> + */

I just noticed that PARA2 check actually checks rank. I think it's important
to implement it (register 0x79c) and uses only TPR10 value, which is already
present.

Best regards,
Jernej

> + if (para->tpr0 & BIT(31)) {
> + val = (para->tpr0 << 1) & 0x3e;
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x78c);
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a4);
> + writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
> + }
> }
>
> writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);