From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B5D7C4332F for ; Tue, 13 Dec 2022 16:51:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 494B585061; Tue, 13 Dec 2022 17:51:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2757185089; Tue, 13 Dec 2022 17:51:43 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 722DC8502D for ; Tue, 13 Dec 2022 17:51:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FAA72F4; Tue, 13 Dec 2022 08:52:19 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E3AD33F5A1; Tue, 13 Dec 2022 08:51:37 -0800 (PST) Date: Tue, 13 Dec 2022 16:51:35 +0000 From: Andre Przywara To: Jernej =?UTF-8?B?xaBrcmFiZWM=?= Cc: jagan@amarulasolutions.com, u-boot@lists.denx.de Subject: Re: [PATCH 4/8] sunxi: Convert H616 DRAM options to single setting Message-ID: <20221213165135.3da3aa49@donnerap.cambridge.arm.com> In-Reply-To: <1912734.PYKUYFuaPT@jernej-laptop> References: <20221211163213.98540-1-jernej.skrabec@gmail.com> <20221211163213.98540-5-jernej.skrabec@gmail.com> <20221212175044.20d78c7e@donnerap.cambridge.arm.com> <1912734.PYKUYFuaPT@jernej-laptop> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tue, 13 Dec 2022 17:23:12 +0100 Jernej =C5=A0krabec wrote: > Hi, >=20 > Dne ponedeljek, 12. december 2022 ob 18:50:44 CET je Andre Przywara=20 > napisal(a): > > On Sun, 11 Dec 2022 17:32:09 +0100 > > Jernej Skrabec wrote: > >=20 > > Hi, > > =20 > > > Vendor DRAM settings use TPR10 parameter to enable various features. > > > There are many mores features that just those that are currently > > > mentioned. Since new will be added later and most are not known, let's > > > reuse value from vendor DRAM driver as-is. This will also help adding > > > support for new boards. =20 > >=20 > > Looks good. I checked that the actual code in > > mctl_phy_bit_delay_compensation() just gets indented (no real changes),= and > > is now guarded by the new checks. > > The values in the _defconfig still result in the same decisions, though > > many are blocked anyway by no one actually calling that bit_delay funct= ion > > at all. (I wonder what happens when we enable it?) =20 >=20 > I'm not sure I understand. Bit delay compensation should be enabled for X= 96=20 > Mate, according to values you send in previous e-mail. But DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION is not set by any (of the two) defconfigs atm, and I don't see this in your t95 (WIP?) branch on github either. So that whole code was completely unused (until now). > In any case, DRAM=20 > configuration looks like a black magic at times, so I would rather stick = to=20 > vendor procedure, especially due to missing register documentation, and n= ot=20 > just randomly enable things which sounds nice. I tried enabling unused=20 > procedures for T95 and either they didn't went through or amount of detec= ted=20 > RAM was lower than presetn. Sure, I was just confused that we have some elaborate code, with values backed by the vendor BSP, but then don't use that. But if it gets used now, it's all fine, I guess. > > One small thing below. > > =20 > > > Signed-off-by: Jernej Skrabec > > > --- > > >=20 > > > .../include/asm/arch-sunxi/dram_sun50i_h616.h | 10 + > > > arch/arm/mach-sunxi/Kconfig | 38 +--- > > > arch/arm/mach-sunxi/dram_sun50i_h616.c | 197 +++++++++-------= -- > > > configs/orangepi_zero2_defconfig | 5 +- > > > 4 files changed, 117 insertions(+), 133 deletions(-) > > >=20 > > > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > > > b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h index > > > c9e1f84bfcdd..b5140c79b70e 100644 > > > --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > > > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > > > @@ -137,6 +137,15 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4= 240); > > >=20 > > > #define MSTR_ACTIVE_RANKS(x) (((x =3D=3D 2) ? 3 : 1) << 24) > > > #define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) > > >=20 > > > +/* TODO: figure out what unknown features do */ > > > +#define TPR10_UNKNOWN_FEAT0 BIT(16) > > > +#define TPR10_UNKNOWN_FEAT1 BIT(17) > > > +#define TPR10_UNKNOWN_FEAT2 BIT(18) =20 > >=20 > > Could you just put the bit number in the macro? Like TPR10_BIT16? That > > both avoids inventing meaningless names, and helps readers to correlate > > code more easily. Or skip the symbol altogether for those and use just > > "BIT(16)" in the code. =20 >=20 > I actually know what these are for now, so I can give much better names.= =20 > However, I still don't know what TPR10_UNKNOWN_FEAT3 does, which is in th= e=20 > last commit, so I'll rework that one to use BIT(30) directly. Great, thanks! Cheers, Andre >=20 > Best regards, > Jernej >=20 > >=20 > > Cheers, > > Andre > > =20 > > > +#define TPR10_WRITE_LEVELING BIT(20) > > > +#define TPR10_READ_CALIBRATION BIT(21) > > > +#define TPR10_READ_TRAINING BIT(22) > > > +#define TPR10_WRITE_TRAINING BIT(23) > > > + > > >=20 > > > struct dram_para { > > > =20 > > > u32 clk; > > > enum sunxi_dram_type type; > > >=20 > > > @@ -147,6 +156,7 @@ struct dram_para { > > >=20 > > > u32 dx_odt; > > > u32 dx_dri; > > > u32 ca_dri; > > >=20 > > > + u32 tpr10; > > >=20 > > > }; > > >=20 > > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig > > > index cad53f19912c..abcbd0fb9061 100644 > > > --- a/arch/arm/mach-sunxi/Kconfig > > > +++ b/arch/arm/mach-sunxi/Kconfig > > > @@ -52,38 +52,6 @@ config DRAM_SUN50I_H616 > > >=20 > > > like H616. > > > =20 > > > if DRAM_SUN50I_H616 > > >=20 > > > -config DRAM_SUN50I_H616_WRITE_LEVELING > > > - bool "H616 DRAM write leveling" > > > - ---help--- > > > - Select this when DRAM on your H616 board needs write leveling. > > > - > > > -config DRAM_SUN50I_H616_READ_CALIBRATION > > > - bool "H616 DRAM read calibration" > > > - ---help--- > > > - Select this when DRAM on your H616 board needs read =20 > calibration. > > > - > > > -config DRAM_SUN50I_H616_READ_TRAINING > > > - bool "H616 DRAM read training" > > > - ---help--- > > > - Select this when DRAM on your H616 board needs read training. > > > - > > > -config DRAM_SUN50I_H616_WRITE_TRAINING > > > - bool "H616 DRAM write training" > > > - ---help--- > > > - Select this when DRAM on your H616 board needs write training. > > > - > > > -config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION > > > - bool "H616 DRAM bit delay compensation" > > > - ---help--- > > > - Select this when DRAM on your H616 board needs bit delay > > > - compensation. > > > - > > > -config DRAM_SUN50I_H616_UNKNOWN_FEATURE > > > - bool "H616 DRAM unknown feature" > > > - ---help--- > > > - Select this when DRAM on your H616 board needs this unknown > > > - feature. > > > - > > >=20 > > > config DRAM_SUN50I_H616_DX_ODT > > > =20 > > > hex "H616 DRAM DX ODT parameter" > > > help > > >=20 > > > @@ -98,6 +66,12 @@ config DRAM_SUN50I_H616_CA_DRI > > >=20 > > > hex "H616 DRAM CA DRI parameter" > > > help > > > =09 > > > CA DRI value from vendor DRAM settings. > > >=20 > > > + > > > +config DRAM_SUN50I_H616_TPR10 > > > + hex "H616 DRAM TPR10 parameter" > > > + help > > > + TPR10 value from vendor DRAM settings. It tells which features > > > + should be configured, like write leveling, read calibration, etc. > > >=20 > > > endif > > > =20 > > > config SUN6I_PRCM > > >=20 > > > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c > > > b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 06a07dfbf9cc..14a01a3c= 4e54 > > > 100644 > > > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c > > > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c > > > @@ -577,109 +577,112 @@ static bool mctl_phy_bit_delay_compensation(s= truct > > > dram_para *para)>=20 > > > u32 *ptr; > > > int i; > > >=20 > > > - clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); > > > - setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8); > > > - clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10); > > > + if (para->tpr10 & TPR10_UNKNOWN_FEAT2) { > > > + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); > > > + setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8); > > > + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x16, ptr); > > > - writel_relaxed(0x16, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0); > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590); > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc); > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x16, ptr); > > > + writel_relaxed(0x16, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4d0); > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x590); > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc); > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x1a, ptr); > > > - writel_relaxed(0x1a, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x1a, ptr); > > > + writel_relaxed(0x1a, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x524); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e4); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x1a, ptr); > > > - writel_relaxed(0x1a, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x1a, ptr); > > > + writel_relaxed(0x1a, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x650); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x710); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x1a, ptr); > > > - writel_relaxed(0x1a, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0); > > > - writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x1a, ptr); > > > + writel_relaxed(0x1a, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a4); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x764); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x6a0); > > > + writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x760); > > >=20 > > > - dmb(); > > > + dmb(); > > >=20 > > > - setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); > > > + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1); > > > + } > > >=20 > > > - /* second part */ > > > - clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80); > > > - clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4); > > > + if (para->tpr10 & TPR10_UNKNOWN_FEAT1) { > > > + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80); > > > + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x10, ptr); > > > - writel_relaxed(0x10, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528); > > > - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8); > > > - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8); > > > - writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x10, ptr); > > > + writel_relaxed(0x10, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x528); > > > + writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x5e8); > > > + writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8); > > > + writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x12, ptr); > > > - writel_relaxed(0x12, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c); > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec); > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c); > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x12, ptr); > > > + writel_relaxed(0x12, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x52c); > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5ec); > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c); > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x12, ptr); > > > - writel_relaxed(0x12, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8); > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768); > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648); > > > - writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x12, ptr); > > > + writel_relaxed(0x12, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x6a8); > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x768); > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648); > > > + writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708); > > >=20 > > > - ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654); > > > - for (i =3D 0; i < 9; i++) { > > > - writel_relaxed(0x14, ptr); > > > - writel_relaxed(0x14, ptr + 0x30); > > > - ptr +=3D 2; > > > - } > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac); > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c); > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c); > > > - writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x75c); > > > + ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654); > > > + for (i =3D 0; i < 9; i++) { > > > + writel_relaxed(0x14, ptr); > > > + writel_relaxed(0x14, ptr + 0x30); > > > + ptr +=3D 2; > > > + } > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x6ac); > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x76c); > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x69c); > > > + writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x75c); > > >=20 > > > - dmb(); > > > + dmb(); > > >=20 > > > - setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80); > > > + setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80); > > > + } > > >=20 > > > return true; > > > =20 > > > } > > >=20 > > > @@ -718,7 +721,7 @@ static bool mctl_phy_init(struct dram_para *para) > > >=20 > > > for (i =3D 0; i < ARRAY_SIZE(phy_init); i++) > > > =09 > > > writel(phy_init[i], &ptr[i]); > > >=20 > > > - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE)) { > > > + if (para->tpr10 & TPR10_UNKNOWN_FEAT0) { > > >=20 > > > ptr =3D (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780); > > > for (i =3D 0; i < 32; i++) > > > =09 > > > writel(0x16, &ptr[i]); > > >=20 > > > @@ -800,7 +803,7 @@ static bool mctl_phy_init(struct dram_para *para) > > >=20 > > > clrbits_le32(&mctl_ctl->rfshctl3, 1); > > > writel(1, &mctl_ctl->swctl); > > >=20 > > > - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING)) { > > > + if (para->tpr10 & TPR10_WRITE_LEVELING) { > > >=20 > > > for (i =3D 0; i < 5; i++) > > > =09 > > > if (mctl_phy_write_leveling(para)) > > > =09 > > > break; > > >=20 > > > @@ -810,7 +813,7 @@ static bool mctl_phy_init(struct dram_para *para) > > >=20 > > > } > > > =09 > > > } > > >=20 > > > - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION)) { > > > + if (para->tpr10 & TPR10_READ_CALIBRATION) { > > >=20 > > > for (i =3D 0; i < 5; i++) =20 > > =20 > > B> if (mctl_phy_read_calibration(para)) =20 > > =20 > > > break; > > >=20 > > > @@ -820,7 +823,7 @@ static bool mctl_phy_init(struct dram_para *para) > > >=20 > > > } > > > =09 > > > } > > >=20 > > > - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_READ_TRAINING)) { > > > + if (para->tpr10 & TPR10_READ_TRAINING) { > > >=20 > > > for (i =3D 0; i < 5; i++) > > > =09 > > > if (mctl_phy_read_training(para)) > > > =09 > > > break; > > >=20 > > > @@ -830,7 +833,7 @@ static bool mctl_phy_init(struct dram_para *para) > > >=20 > > > } > > > =09 > > > } > > >=20 > > > - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING)) { > > > + if (para->tpr10 & TPR10_WRITE_TRAINING) { > > >=20 > > > for (i =3D 0; i < 5; i++) > > > =09 > > > if (mctl_phy_write_training(para)) > > > =09 > > > break; > > >=20 > > > @@ -840,8 +843,7 @@ static bool mctl_phy_init(struct dram_para *para) > > >=20 > > > } > > > =09 > > > } > > >=20 > > > - if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION)) > > > - mctl_phy_bit_delay_compensation(para); > > > + mctl_phy_bit_delay_compensation(para); > > >=20 > > > clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 4); > > >=20 > > > @@ -1022,6 +1024,7 @@ unsigned long sunxi_dram_init(void) > > >=20 > > > .dx_odt =3D CONFIG_DRAM_SUN50I_H616_DX_ODT, > > > .dx_dri =3D CONFIG_DRAM_SUN50I_H616_DX_DRI, > > > .ca_dri =3D CONFIG_DRAM_SUN50I_H616_CA_DRI, > > >=20 > > > + .tpr10 =3D CONFIG_DRAM_SUN50I_H616_TPR10, > > >=20 > > > }; > > > unsigned long size; > > >=20 > > > diff --git a/configs/orangepi_zero2_defconfig > > > b/configs/orangepi_zero2_defconfig index ca398faef1d3..f2024a2502c7 > > > 100644 > > > --- a/configs/orangepi_zero2_defconfig > > > +++ b/configs/orangepi_zero2_defconfig > > > @@ -2,13 +2,10 @@ CONFIG_ARM=3Dy > > >=20 > > > CONFIG_ARCH_SUNXI=3Dy > > > CONFIG_DEFAULT_DEVICE_TREE=3D"sun50i-h616-orangepi-zero2" > > > CONFIG_SPL=3Dy > > >=20 > > > -CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING=3Dy > > > -CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=3Dy > > > -CONFIG_DRAM_SUN50I_H616_READ_TRAINING=3Dy > > > -CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=3Dy > > >=20 > > > CONFIG_DRAM_SUN50I_H616_DX_ODT=3D0x8080808 > > > CONFIG_DRAM_SUN50I_H616_DX_DRI=3D0xe0e0e0e > > > CONFIG_DRAM_SUN50I_H616_CA_DRI=3D0xe0e > > >=20 > > > +CONFIG_DRAM_SUN50I_H616_TPR10=3D0xf83438 > > >=20 > > > CONFIG_MACH_SUN50I_H616=3Dy > > > CONFIG_MMC0_CD_PIN=3D"PF6" > > > CONFIG_R_I2C_ENABLE=3Dy =20 >=20 >=20 >=20 >=20