From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5E65C4332F for ; Tue, 13 Dec 2022 20:09:30 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9DD208453A; Tue, 13 Dec 2022 21:09:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id C183A84EA1; Tue, 13 Dec 2022 21:09:25 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 1AC4F83897 for ; Tue, 13 Dec 2022 21:09:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDDEB2F4; Tue, 13 Dec 2022 12:10:02 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C315A3F73B; Tue, 13 Dec 2022 12:09:21 -0800 (PST) Date: Tue, 13 Dec 2022 20:07:47 +0000 From: Andre Przywara To: Samuel Holland Cc: Jagan Teki , u-boot@lists.denx.de Subject: Re: [PATCH v2] pinctrl: sunxi: Add P2WI and RSB pinmuxes Message-ID: <20221213200747.4fbc10a6@slackpad.lan> In-Reply-To: <20221118042228.48294-1-samuel@sholland.org> References: <20221118042228.48294-1-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Thu, 17 Nov 2022 22:22:27 -0600 Samuel Holland wrote: > P2WI and RSB are used to communicate with a PMIC. Most SoCs have only > one possible pinmux. F1C100s has two possibilities, with different mux > values, so omit it until some board needs one of them. > > Signed-off-by: Samuel Holland Compared against the manuals. Reviewed-by: Andre Przywara Cheers, Andre > --- > > Changes in v2: > - Fix pin list comment for A80 entry > > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index 061104be056..c4fbda7a925 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -338,6 +338,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > { "s_i2c", 2 }, /* PL0-PL1 */ > + { "s_p2wi", 3 }, /* PL0-PL1 */ > { "s_uart", 2 }, /* PL2-PL3 */ > }; > > @@ -404,6 +405,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > { "s_i2c", 3 }, /* PL0-PL1 */ > + { "s_rsb", 2 }, /* PL0-PL1 */ > { "s_uart", 2 }, /* PL2-PL3 */ > }; > > @@ -469,6 +471,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > { "s_i2c", 2 }, /* PL8-PL9 */ > + { "s_rsb", 2 }, /* PL0-PL1 */ > { "s_uart", 2 }, /* PL2-PL3 */ > }; > > @@ -574,6 +577,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = { > { "gpio_out", 1 }, > { "s_i2c0", 2 }, /* PN0-PN1 */ > { "s_i2c1", 3 }, /* PM8-PM9 */ > + { "s_rsb", 3 }, /* PN0-PN1 */ > { "s_uart", 3 }, /* PL0-PL1 */ > }; > > @@ -615,6 +619,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > { "s_i2c", 2 }, /* PL8-PL9 */ > + { "s_rsb", 2 }, /* PL0-PL1 */ > { "s_uart", 2 }, /* PL2-PL3 */ > }; > > @@ -680,6 +685,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > { "s_i2c", 3 }, /* PL0-PL1 */ > + { "s_rsb", 2 }, /* PL0-PL1 */ > { "s_uart", 2 }, /* PL2-PL3 */ > }; > > @@ -717,6 +723,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = { > { "gpio_in", 0 }, > { "gpio_out", 1 }, > { "s_i2c", 3 }, /* PL0-PL1 */ > + { "s_rsb", 2 }, /* PL0-PL1 */ > { "s_uart", 2 }, /* PL2-PL3 */ > }; >