* [PATCH v2] pinctrl: sunxi: Add P2WI and RSB pinmuxes
@ 2022-11-18 4:22 Samuel Holland
2022-12-13 20:07 ` Andre Przywara
0 siblings, 1 reply; 2+ messages in thread
From: Samuel Holland @ 2022-11-18 4:22 UTC (permalink / raw)
To: Andre Przywara, Jagan Teki; +Cc: Samuel Holland, u-boot
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes in v2:
- Fix pin list comment for A80 entry
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 061104be056..c4fbda7a925 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -338,6 +338,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL0-PL1 */
+ { "s_p2wi", 3 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -404,6 +405,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -469,6 +471,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -574,6 +577,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
{ "gpio_out", 1 },
{ "s_i2c0", 2 }, /* PN0-PN1 */
{ "s_i2c1", 3 }, /* PM8-PM9 */
+ { "s_rsb", 3 }, /* PN0-PN1 */
{ "s_uart", 3 }, /* PL0-PL1 */
};
@@ -615,6 +619,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 2 }, /* PL8-PL9 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -680,6 +685,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
@@ -717,6 +723,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
{ "gpio_in", 0 },
{ "gpio_out", 1 },
{ "s_i2c", 3 }, /* PL0-PL1 */
+ { "s_rsb", 2 }, /* PL0-PL1 */
{ "s_uart", 2 }, /* PL2-PL3 */
};
--
2.37.4
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v2] pinctrl: sunxi: Add P2WI and RSB pinmuxes
2022-11-18 4:22 [PATCH v2] pinctrl: sunxi: Add P2WI and RSB pinmuxes Samuel Holland
@ 2022-12-13 20:07 ` Andre Przywara
0 siblings, 0 replies; 2+ messages in thread
From: Andre Przywara @ 2022-12-13 20:07 UTC (permalink / raw)
To: Samuel Holland; +Cc: Jagan Teki, u-boot
On Thu, 17 Nov 2022 22:22:27 -0600
Samuel Holland <samuel@sholland.org> wrote:
> P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
> one possible pinmux. F1C100s has two possibilities, with different mux
> values, so omit it until some board needs one of them.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Compared against the manuals.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> Changes in v2:
> - Fix pin list comment for A80 entry
>
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 061104be056..c4fbda7a925 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -338,6 +338,7 @@ static const struct sunxi_pinctrl_function sun6i_a31_r_pinctrl_functions[] = {
> { "gpio_in", 0 },
> { "gpio_out", 1 },
> { "s_i2c", 2 }, /* PL0-PL1 */
> + { "s_p2wi", 3 }, /* PL0-PL1 */
> { "s_uart", 2 }, /* PL2-PL3 */
> };
>
> @@ -404,6 +405,7 @@ static const struct sunxi_pinctrl_function sun8i_a23_r_pinctrl_functions[] = {
> { "gpio_in", 0 },
> { "gpio_out", 1 },
> { "s_i2c", 3 }, /* PL0-PL1 */
> + { "s_rsb", 2 }, /* PL0-PL1 */
> { "s_uart", 2 }, /* PL2-PL3 */
> };
>
> @@ -469,6 +471,7 @@ static const struct sunxi_pinctrl_function sun8i_a83t_r_pinctrl_functions[] = {
> { "gpio_in", 0 },
> { "gpio_out", 1 },
> { "s_i2c", 2 }, /* PL8-PL9 */
> + { "s_rsb", 2 }, /* PL0-PL1 */
> { "s_uart", 2 }, /* PL2-PL3 */
> };
>
> @@ -574,6 +577,7 @@ static const struct sunxi_pinctrl_function sun9i_a80_r_pinctrl_functions[] = {
> { "gpio_out", 1 },
> { "s_i2c0", 2 }, /* PN0-PN1 */
> { "s_i2c1", 3 }, /* PM8-PM9 */
> + { "s_rsb", 3 }, /* PN0-PN1 */
> { "s_uart", 3 }, /* PL0-PL1 */
> };
>
> @@ -615,6 +619,7 @@ static const struct sunxi_pinctrl_function sun50i_a64_r_pinctrl_functions[] = {
> { "gpio_in", 0 },
> { "gpio_out", 1 },
> { "s_i2c", 2 }, /* PL8-PL9 */
> + { "s_rsb", 2 }, /* PL0-PL1 */
> { "s_uart", 2 }, /* PL2-PL3 */
> };
>
> @@ -680,6 +685,7 @@ static const struct sunxi_pinctrl_function sun50i_h6_r_pinctrl_functions[] = {
> { "gpio_in", 0 },
> { "gpio_out", 1 },
> { "s_i2c", 3 }, /* PL0-PL1 */
> + { "s_rsb", 2 }, /* PL0-PL1 */
> { "s_uart", 2 }, /* PL2-PL3 */
> };
>
> @@ -717,6 +723,7 @@ static const struct sunxi_pinctrl_function sun50i_h616_r_pinctrl_functions[] = {
> { "gpio_in", 0 },
> { "gpio_out", 1 },
> { "s_i2c", 3 }, /* PL0-PL1 */
> + { "s_rsb", 2 }, /* PL0-PL1 */
> { "s_uart", 2 }, /* PL2-PL3 */
> };
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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