From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B138C4332F for ; Sat, 24 Dec 2022 01:16:09 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 56C35854C2; Sat, 24 Dec 2022 02:15:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="yglL7NUy"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1D69B854C7; Sat, 24 Dec 2022 02:15:46 +0100 (CET) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0919E8523F for ; Sat, 24 Dec 2022 02:15:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=bb@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BO1Fc6L074414; Fri, 23 Dec 2022 19:15:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671844539; bh=Myzw3zdIyhInvQZKh0K83zcPMeKY3QRgg2DIEywnoeI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yglL7NUy54bPVYhmPo5v9EkCNU2v2CVk0lzI7YZz1/yT0CUVmvopkkaZXMknOj6+X Lp4WP7zG4+E64eQoMnE0y46LgwYFeGucLrDFv6R24iNiMmUEITJv36dDMBdRovmsPf FWwadCUXZArddBOYsdVGl/06zv5CGsTV3jjid/oI= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BO1FcTu028614 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Dec 2022 19:15:38 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 23 Dec 2022 19:15:38 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 23 Dec 2022 19:15:38 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BO1FcFB127889; Fri, 23 Dec 2022 19:15:38 -0600 From: Bryan Brattlof To: Tom Rini , Vignesh Raghavendra , Andrew Davis , Judith Mendez , Kamlesh Gurudasani CC: UBoot Mailing List , Bryan Brattlof Subject: [PATCH 3/5] arm: mach-k3: copy bootindex to OCRAM for main domain SPL Date: Fri, 23 Dec 2022 19:15:23 -0600 Message-ID: <20221224011525.4696-4-bb@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221224011525.4696-1-bb@ti.com> References: <20221224011525.4696-1-bb@ti.com> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4035; i=bb@ti.com; h=from:subject; bh=kZ6T9X3cjG2w6812VaUkpCNmuFJCQHOiiykVLYO/Xvg=; b=owNCWmg5MUFZJlNZm0VYuwAAZX///rbt/vf3PIP//727v57m7g//+/W5nv/3dH9/w/741XWwARsY HagB6mhoAAANAAAyNBoADQAAAGIAAAPUAANAGho2o09RtRpieSZPJ6ogDRoNNAHqA9TQGgaAAaBp6h o0ANPUaBkDT1DQaepkGQA9EBptQNNDTQAHqAHqHqCGh6mjTRkGjINGQNNGRo00YEBoNAwE0ZAAaGjI AMjQ00GQMgAaGgBhBiNAAALQlavBpwIUKGISICbMS4ASVYxIZ8bdoLGX8UdqJCzYFqkXq6aYRrNnPa FUtfEzM7KMEhE0COyFQiqmzcHT0cJBF5CMs9q938XYZuVyByKFp4M4MIhVGqsczbic4fKrPBz5r6J5 tdcbOyfU1MWiPIgBqKdIIutFcpZA5yvr1AT4iDJ/ofEFhccDMGeFhcqDKXgt5NqlC07tL2Gz6elRLF A4QBIXjmoLhiGvOGVpSL30qZhKmym5L50oO86GOacSc9ApT++HUpkLpDnXoXmrRTBIZiGRoghj/XCT 6cYQzZJWUleVjrTUT8ezfLpFDXN3SjUkV6uSZnbYXZrCQNrFK4uMDLRpB7co5sj2zHyCPuqrSeFQX5 c5Qn8cWjEYpDUFFq8ZehtDL9UEgKBYiV9csYEICheEsATJZ3Y8UBiiTHgf4u5IpwoSE2irF2A= X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Texas Instruments has begun enabling security settings on the SoCs it produces to instruct ROM and TIFS to begin protecting the Security Management Subsystem (SMS) from other binaries we load into the chip by default. One way ROM and TIFS do this is by enabling firewalls to protect the OCSRAM and HSM RAM regions they're using during bootup. The HSM RAM the wakeup SPL is in is firewalled by TIFS to protect itself from the main domain applications. This means the 'bootindex' value in HSM RAM, left by ROM to indicate if we're using the primary or secondary boot-method, must be moved to OCSRAM (that TIFS has open for us) before we make the jump to the main domain so the main domain's bootloaders can keep access to this information. Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/Kconfig | 4 +++- arch/arm/mach-k3/am62a7_init.c | 16 ++++++++++++++-- arch/arm/mach-k3/include/mach/am62a_hardware.h | 17 ++++++++++++++++- 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 87da6b49ee6b7..a8c3a593d5704 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -69,7 +69,9 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 - default 0x43c3f290 if SOC_K3_AM625 || SOC_K3_AM62A7 + default 0x43c3f290 if SOC_K3_AM625 + default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R + default 0x7000f290 if SOC_K3_AM62A7 && ARM64 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c index e9569f0d26418..02da24a3d6f0d 100644 --- a/arch/arm/mach-k3/am62a7_init.c +++ b/arch/arm/mach-k3/am62a7_init.c @@ -25,8 +25,11 @@ static struct rom_extended_boot_data bootdata __section(".data"); static void store_boot_info_from_rom(void) { bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); - memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, - sizeof(struct rom_extended_boot_data)); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); + } } static void ctrl_mmr_unlock(void) @@ -123,6 +126,15 @@ void board_init_f(ulong dummy) k3_sysfw_loader(true, NULL, NULL); #endif +#if defined(CONFIG_CPU_V7R) + /* + * Relocate boot information to OCRAM (after TIFS has opend this + * region for us) so the next bootloader stages can keep access to + * primary vs backup bootmodes. + */ + writel(bootindex, K3_BOOT_PARAM_TABLE_INDEX_OCRAM); +#endif + /* * Force probe of clk_k3 driver here to ensure basic default clock * configuration is always done. diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h index 52b0d9b3cb95c..13bf50f147b1e 100644 --- a/arch/arm/mach-k3/include/mach/am62a_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -68,7 +68,22 @@ #define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0 -/* Use Last 2K as Scratch pad */ +#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290 + +/* + * During the boot process ROM will kill anything that writes to OCSRAM. + * This means the wakeup SPL cannot use this region during boot. To + * complicate things, TIFS will set a firewall between HSM RAM and the + * main domain. + * + * So, during the wakeup SPL, we will need to store the EEPROM data + * somewhere in HSM RAM, and the main domain's SPL will need to store it + * somewhere in OCSRAM + */ +#ifdef CONFIG_CPU_V7R +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000 +#else #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001 +#endif /* CONFIG_CPU_V7R */ #endif /* __ASM_ARCH_AM62A_HARDWARE_H */ -- 2.39.0