From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 674F1C4708E for ; Wed, 4 Jan 2023 00:41:13 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ED92585569; Wed, 4 Jan 2023 01:40:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 3032785557; Wed, 4 Jan 2023 01:40:21 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id DEB6885560 for ; Wed, 4 Jan 2023 01:40:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 071181063; Tue, 3 Jan 2023 16:40:56 -0800 (PST) Received: from slackpad.lan (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A74873F71A; Tue, 3 Jan 2023 16:40:13 -0800 (PST) Date: Wed, 4 Jan 2023 00:36:41 +0000 From: Andre Przywara To: Jernej Skrabec Cc: jagan@amarulasolutions.com, u-boot@lists.denx.de Subject: Re: [PATCH 3/8] sunxi: parameterize H616 DRAM ODT values Message-ID: <20230104003641.0683c235@slackpad.lan> In-Reply-To: <20221211163213.98540-4-jernej.skrabec@gmail.com> References: <20221211163213.98540-1-jernej.skrabec@gmail.com> <20221211163213.98540-4-jernej.skrabec@gmail.com> Organization: Arm Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Sun, 11 Dec 2022 17:32:08 +0100 Jernej Skrabec wrote: Hi Jernej, > While ODT values for same memory type are similar, they are not > necessary the same. Let's parameterize them and make parameter same as > in vendor DRAM settings. That way it will be easy to introduce new board > support. checked that this results in the same parameters to writel(). One small thing below: > > Signed-off-by: Jernej Skrabec > --- > .../include/asm/arch-sunxi/dram_sun50i_h616.h | 3 + > arch/arm/mach-sunxi/Kconfig | 15 +++++ > arch/arm/mach-sunxi/dram_sun50i_h616.c | 59 ++++++++++++------- > configs/orangepi_zero2_defconfig | 3 + > 4 files changed, 58 insertions(+), 22 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > index 134679d55205..c9e1f84bfcdd 100644 > --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > @@ -144,6 +144,9 @@ struct dram_para { > u8 rows; > u8 ranks; > u8 bus_full_width; > + u32 dx_odt; > + u32 dx_dri; > + u32 ca_dri; > }; > > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig > index dbe6005daab1..cad53f19912c 100644 > --- a/arch/arm/mach-sunxi/Kconfig > +++ b/arch/arm/mach-sunxi/Kconfig > @@ -83,6 +83,21 @@ config DRAM_SUN50I_H616_UNKNOWN_FEATURE > ---help--- > Select this when DRAM on your H616 board needs this unknown > feature. > + > +config DRAM_SUN50I_H616_DX_ODT > + hex "H616 DRAM DX ODT parameter" > + help > + DX ODT value from vendor DRAM settings. > + > +config DRAM_SUN50I_H616_DX_DRI > + hex "H616 DRAM DX DRI parameter" > + help > + DX DRI value from vendor DRAM settings. > + > +config DRAM_SUN50I_H616_CA_DRI > + hex "H616 DRAM CA DRI parameter" > + help > + CA DRI value from vendor DRAM settings. > endif > > config SUN6I_PRCM > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c > index 49983bf7a1b8..06a07dfbf9cc 100644 > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c > @@ -234,37 +234,49 @@ static const u8 phy_init[] = { > 0x09, 0x05, 0x18 > }; > > -static void mctl_phy_configure_odt(void) > +static void mctl_phy_configure_odt(struct dram_para *para) > { > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x388); > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x38c); > + unsigned int val; > > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3c8); > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x3cc); > + val = para->dx_dri & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c); > > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x408); > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x40c); > + val = (para->dx_dri >> 8) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc); > > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x448); > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x44c); > + val = (para->dx_dri >> 16) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c); > > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x340); > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x344); > + val = (para->dx_dri >> 24) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c); > > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x348); > - writel_relaxed(0xe, SUNXI_DRAM_PHY0_BASE + 0x34c); > + val = para->ca_dri & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344); > > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x380); > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x384); > + val = (para->ca_dri >> 8) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c); > > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c0); > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x3c4); > + val = para->dx_odt & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384); > > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x400); > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x404); > + val = (para->dx_odt >> 8) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4); > > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x440); > - writel_relaxed(0x8, SUNXI_DRAM_PHY0_BASE + 0x444); > + val = (para->dx_odt >> 16) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404); > + > + val = (para->dx_odt >> 24) & 0x1f; > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440); > + writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444); > > dmb(); > } > @@ -722,7 +734,7 @@ static bool mctl_phy_init(struct dram_para *para) > writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c); > > if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) > - mctl_phy_configure_odt(); > + mctl_phy_configure_odt(para); > > clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa); > > @@ -1007,6 +1019,9 @@ unsigned long sunxi_dram_init(void) > struct dram_para para = { > .clk = CONFIG_DRAM_CLK, > .type = SUNXI_DRAM_TYPE_DDR3, > + .dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT, > + .dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI, > + .ca_dri = CONFIG_DRAM_SUN50I_H616_CA_DRI, > }; > unsigned long size; > > diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig > index 877eccf31bd6..ca398faef1d3 100644 > --- a/configs/orangepi_zero2_defconfig > +++ b/configs/orangepi_zero2_defconfig > @@ -6,6 +6,9 @@ CONFIG_DRAM_SUN50I_H616_WRITE_LEVELING=y > CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION=y > CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y > CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y > +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x8080808 > +CONFIG_DRAM_SUN50I_H616_DX_DRI=0xe0e0e0e > +CONFIG_DRAM_SUN50I_H616_CA_DRI=0xe0e Can you make those values 8 nibbles and 4 nibbles long (so starting with a 0)? It's somewhat confusing to read like this, it *looks* like a 32-bit value, but it's actually only 28 bits wide. This gets confusing when matching up values against dumps or a hex editor. With that fixed: Reviewed-by: Andre Przywara Cheers, Andre > CONFIG_MACH_SUN50I_H616=y > CONFIG_MMC0_CD_PIN="PF6" > CONFIG_R_I2C_ENABLE=y