From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53160C54EBD for ; Fri, 6 Jan 2023 18:03:06 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 58AEE853BE; Fri, 6 Jan 2023 19:03:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="UxDxGuCb"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 45010853E0; Fri, 6 Jan 2023 19:03:01 +0100 (CET) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F0F2F85368 for ; Fri, 6 Jan 2023 19:02:57 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=afd@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 306I2pLR041633; Fri, 6 Jan 2023 12:02:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1673028171; bh=IJTv+T/LMjJM6sa2f8xwRUwfkBh/fyFATdM9KCSYRpg=; h=From:To:CC:Subject:Date; b=UxDxGuCbBJjr0+JRtwdsnbVRYkLoPBKbxiJhxzsCznZEeeL4kjd7g3VDQ8F9BLxMo d5O1CjCNt9sez+gGvKCSmUv6MuC5malS+RB238je083whk/Ex2ztAzJ4qD7tsdIZZh eM5eUz/lx4DPNZm1pBFm8MX7wlhV0NIrrQYhlPKM= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 306I2ptp025258 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 6 Jan 2023 12:02:51 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 6 Jan 2023 12:02:51 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 6 Jan 2023 12:02:51 -0600 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 306I2p3N008045; Fri, 6 Jan 2023 12:02:51 -0600 From: Andrew Davis To: Simon Glass , Tom Rini , CC: Andrew Davis Subject: [PATCH] common: bouncebuf: Use dma-mapping for cache ops Date: Fri, 6 Jan 2023 12:02:50 -0600 Message-ID: <20230106180250.22348-1-afd@ti.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This matches how this would be done in Linux and these functions do the alignment for us which makes the code look cleaner. Signed-off-by: Andrew Davis --- common/bouncebuf.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/common/bouncebuf.c b/common/bouncebuf.c index 6d98920de66..93a35668cc2 100644 --- a/common/bouncebuf.c +++ b/common/bouncebuf.c @@ -12,6 +12,7 @@ #include #include #include +#include static int addr_aligned(struct bounce_buffer *state) { @@ -59,9 +60,9 @@ int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data, * Flush data to RAM so DMA reads can pick it up, * and any CPU writebacks don't race with DMA writes */ - flush_dcache_range((unsigned long)state->bounce_buffer, - (unsigned long)(state->bounce_buffer) + - state->len_aligned); + dma_map_single(state->bounce_buffer, + state->len_aligned, + DMA_BIDIRECTIONAL); return 0; } @@ -78,9 +79,9 @@ int bounce_buffer_stop(struct bounce_buffer *state) { if (state->flags & GEN_BB_WRITE) { /* Invalidate cache so that CPU can see any newly DMA'd data */ - invalidate_dcache_range((unsigned long)state->bounce_buffer, - (unsigned long)(state->bounce_buffer) + - state->len_aligned); + dma_unmap_single((dma_addr_t)state->bounce_buffer, + state->len_aligned, + DMA_BIDIRECTIONAL); } if (state->bounce_buffer == state->user_buffer) -- 2.38.1