From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5075C38142 for ; Thu, 19 Jan 2023 07:06:12 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A05D585640; Thu, 19 Jan 2023 08:06:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id AE0D785651; Thu, 19 Jan 2023 08:06:09 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 52F7585482 for ; Thu, 19 Jan 2023 08:06:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peterlin@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 30J75vww090743 for ; Thu, 19 Jan 2023 15:05:57 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.158) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 19 Jan 2023 15:05:55 +0800 From: Yu Chien Peter Lin To: CC: , , Yu Chien Peter Lin Subject: [PATCH 00/11] cache operation cleanups for Andes AE350 platform Date: Thu, 19 Jan 2023 15:05:33 +0800 Message-ID: <20230119070544.7423-1-peterlin@andestech.com> X-Mailer: git-send-email 2.38.0.68.ge85701b4af.dirty MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.0.15.158] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 30J75vww090743 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This patchset is intended to enable L2-cache in U-boot SPL, along with cache operations cleanup for AE350 platforms. Leo Yu-Chi Liang (1): riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" Yu Chien Peter Lin (10): riscv: global_data.h: Correct the comment for PLICSW board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() riscv: ae350: dts: Update L2 cache compatible string riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL configs: ae350: Enable v5l2 cache for AE350 platforms configs: ae350: Increase maximum retry count for AE350 platforms configs: ae350: Display CPU and board info for AE350 platforms driver: cache-v5l2: Fix type casting warning on RV32 arch/riscv/cpu/ax25/Kconfig | 10 -- arch/riscv/cpu/ax25/cache.c | 120 ++++++++---------------- arch/riscv/cpu/ax25/cpu.c | 46 +++------ arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++ arch/riscv/include/asm/global_data.h | 2 +- board/AndesTech/ax25-ae350/ax25-ae350.c | 17 ++-- configs/ae350_rv32_defconfig | 4 + configs/ae350_rv32_spl_defconfig | 6 ++ configs/ae350_rv32_spl_xip_defconfig | 6 ++ configs/ae350_rv32_xip_defconfig | 4 + configs/ae350_rv64_defconfig | 4 + configs/ae350_rv64_spl_defconfig | 6 ++ configs/ae350_rv64_spl_xip_defconfig | 6 ++ configs/ae350_rv64_xip_defconfig | 4 + drivers/cache/Kconfig | 1 - drivers/cache/cache-v5l2.c | 36 +++++-- 18 files changed, 158 insertions(+), 147 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h -- 2.34.1